LAN9115 datasheet(63/114 Pages) MICROCHIP

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DS00002269A-page 63

LAN9115

5.3.4

INT_EN—INTERRUPT ENABLE REGISTER

This register contains the interrupt masks for IRQ. Writing 1 to any of the bits enables the corresponding interrupt as a

source for IRQ. Bits in the INT_STS register will still reflect the status of the interrupt source regardless of whether the

source is enabled as an interrupt in this register.

Transmitter Error (TXE). When generated, indicates that the transmitter

has encountered an error. Please refer to Section 3.13.7, "Transmitter

Errors," on page 46, for a description of the conditions that will cause a

TXE.

R/WC

12-11

Reserved

TX Data FIFO Overrun Interrupt (TDFO). Generated when the TX data

FIFO is full, and another write is attempted.

R/WC

TX Data FIFO Available Interrupt (TDFA). Generated when the TX data

FIFO available space is greater than the programmed level.

R/WC

TX Status FIFO Full Interrupt (TSFF). Generated when the TX Status

FIFO is full.

R/WC

TX Status FIFO Level Interrupt (TSFL). Generated when the TX Status

FIFO reaches the programmed level.

R/WC

RX Dropped Frame Interrupt (RXDF_INT). This interrupt is issued

whenever a receive frame is dropped.

R/WC

Reserved

RX Status FIFO Full Interrupt (RSFF). Generated when the RX Status

FIFO is full.

R/WC

RX Status FIFO Level Interrupt (RSFL). Generated when the RX Status

FIFO reaches the programmed level.

R/WC

2-0

GPIO [2:0] (GPIOx_INT). Interrupts are generated from the GPIO’s. These

interrupts are configured through the GPIO_CFG register.

R/WC

000

Offset:

5Ch

Size:

32 bits

Bits

Description

Type

Default

Software Interrupt (SW_INT_EN)

R/W

30:26

Reserved

TX Stopped Interrupt Enable (TXSTOP_INT_EN)

R/W

RX Stopped Interrupt Enable (RXSTOP_INT_EN)

R/W

RX Dropped Frame Counter Halfway Interrupt Enable

(RXDFH_INT_EN).

R/W

Reserved

TX IOC Interrupt Enable (TIOC_INT_EN)

R/W

RX DMA Interrupt (RXD_INT).

R/W

GP Timer (GPT_INT_EN)

R/W

PHY (PHY_INT_EN)

R/W

Power Management Event Interrupt Enable (PME_INT_EN)

R/W

TX Status FIFO Overflow (TXSO_EN)

R/W

Receive Watchdog Time-out Interrupt (RWT_INT_EN)

R/W

Receiver Error Interrupt (RXE_INT_EN)

R/W

Transmitter Error Interrupt (TXE_INT_EN)

R/W

12-11

Reserved

TX Data FIFO Overrun Interrupt (TDFO_INT_EN)

R/W

Bits

Description

Type

Default

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