LAN9115 datasheet(34/114 Pages) MICROCHIP

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LAN9115

DS00002269A-page 34

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3.11.4

SOFT RESET (SRST)

Soft reset is initiated by writing a ‘1’ to bit 0 of the HW_CFG register (SRST). This self-clearing bit will return to ‘0’ after

approximately 2

s, at which time the Soft Reset is complete. Soft reset does not clear control register bits marked as

NASR.

APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) immediately,

(within 2

s). If the software driver polls this bit and it is not set within 100ms, then an error

condition occurred.

3.11.5

PHY RESET TIMING

The following sections and tables specify the operation and time required for the internal PHY to become operational

after various resets or when returning from the reduced power state.

3.11.5.1

PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST)

The PHY soft reset is initiated by writing a ‘1’ to bit 10 of the PMT_CTRL register (PHY_RST). This self-clearing bit will

return to ‘0’ after approximately 100

s, at which time the PHY reset is complete.

3.11.5.2

PHY Soft Reset via PHY Basic Control Register (PHY Reg. 0.15)

The PHY Reg. 0.15 Soft Reset is initiated by writing a ‘1’ to bit 15 of the PHY’s Basic Control Register. This self-clearing

bit will return to ‘0’ at which time the PHY reset is complete.

3.12

MII Interface - External MII Switching

There are two mechanisms that are used to switch between the internal PHY and the external MII port.

• A LAN driver or other software controlled mechanism is used to control the PHY_CLK_SEL[1:0] bits described in

Section 5.3.9, "HW_CFG—Hardware Configuration Register" that provides glitch-free MII clock switching. This

mechanism allows the host processor to disable (gate) the RX_CLK and TX_CLK clocks from both the internal

PHY and the external MII port, and switch the clock sources once they have stopped. After switching the clocks,

the LAN9115 transmitter and receiver can be re-enabled.

• A simple multiplexor that, with the exception of the SMI bus and the MII clocks, will switch the remaining MII sig-

nals. This multiplexor is controlled by the EXT_PHY_EN bit described in Section 5.3.9, "HW_CFG—Hardware

Configuration Register".

3.12.1

SMI SWITCHING

The Serial Management Interface (SMI) port can be switched between the internal PHY and external MII ports based

on the settings of the SMI_SEL bit described in Section 5.3.9, "HW_CFG—Hardware Configuration Register". The SMI

port can be switched independent of the setting of the other MII signals.

APPLICATION NOTE: The user is cautioned to not switch the SMI port while an SMI transaction is in progress.

3.12.2

MII CLOCK SWITCHING

The LAN9115 supports dynamic switching between the integrated internal PHY and the external MII port which can con-

nect to an external MII compatible Ethernet PHY device.

The remaining MII signals, with the exception of the SMI port, are switched using a simple multiplexor controlled by the

EXT_PHY_SEL bit described in Section 5.3.9, "HW_CFG—Hardware Configuration Register". It is required that the MII

clocks be disabled before the other MII signals are switched.

The steps outlined in the flow diagram in Figure 3-12, "MII Switching Procedure", detail the required procedure for

switching the MII port, including the MII clocks. These steps must be followed in order to ensure clean switching of the

MII ports.

Using the SMI interface, both the internal PHY, and the external PHY must be placed in a stable state. For each device

generating a TX_CLK or RX_CLK, this clock must be stable and glitch-free before the switch can be made. If either

device is not generating a TX_CLK or RX_CLK, this clock must remain off until the switch is complete. In either case

the TX_CLK and RX_CLK must be stable and glitch-free for the device that will be selected after the switch. The follow-

ing must be done prior to a switch:

• The LAN9115 Transmitter must be halted.

• The halting of the LAN9115 transmitter must be complete

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