AT25QL641 datasheet(76/77 Pages) DIALOG

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AT25QL641

DS-25QL641–130E–10/2018

11.

Revision History

11.1

Errata:

Appendix A

1. If Status Register-2 CMP bit is 0, and Status Register-1 bits {SEC,TB,BP2,BP1,BP} are {1,0,0,0,1}, address 7FF000h-

7FFFFFh is protected from any Program or Erase commands. However, this setting does not protect the rest of Sector

127 or the rest of Block 255 from 64Kbit or 32kbit Block Erase commands. If a 64Kbit Block Erase Command is issued to

Sector 127, address 7F0000h-7FEFFFh will be erased. If a 32Kbit Block Erase Command is issued to Block 255,

address 7F8000h-7FEFFFh will be erased.

Workaround: If this protection bit combination is used and the behavior described in Note 3 is required, avoid using

64Kbit or 32kbit Block Erase commands for this specific memory region.

2. If Status Register-2 CMP bit is 1, and Status Register-1 bits {SEC,TB,BP2,BP1,BP} are {1,1,0,0,1}, address 001000h-

7FFFFFh is protected from any Program or Erase commands. However, this setting does not protect the rest of Sector 0

or the rest of Block 0 from 64Kbit or 32kbit Block Erase commands. If a 64Kbit Block Erase Command is issued to Sector

0, address 000000h-000FFFh will be erased. If a 32Kbit Block Erase Command is issued to Block 0, address 000000h-

000FFFh will be erased.

Workaround: If this protection bit combination is used and the behavior described in Note 3 is required, avoid using

64Kbit or 32kbit Block Erase commands for this specific memory region.

Revision

Date

Change Description

12/2016

Initial release of AT25QL641 datasheet.

02/2017

Updated Note 1 on Table 8.1.

05/2017

Updated Table 1-1 (WP pin description). Updated 5.1 (Write Protect Features). Updated

Tables 6-1 and 6-2. Restored Sector and Block Protect descriptions. Restored Status

Errata 11.1.

11/2017

Removed references to 133 MHz option. Removed RESET option. Removed 18-WLCSP and

24-ball BGA package options. Removed references to ACC feature.

10/2018

Added 133 MHz frequency option to document.

Updated maximum frequency to 133 MHz on page 1.

Updated frequencies in Section 1.

Updated formatting of all tables in document.

Updated Word Read Quad I/O instruction diagram in Figure 7-50.

Updated frequency in Burst Read with Wrap instruction in Figure 7-54.

Updated tables in Section 7.33, Set Read Parameters (C0h).

Updated AC Electrical Characteristics table in Table 8-7 with 133 MHz option.

Clarified frequency and timing parameters for the 03h and 0Bh instructions in Table 8-7.

Updated ordering code table in Section 9.1.

Removed DWF package.

Updated maximum continuous data transfer rate from 52 Mbps to 66 Mbps on page 1.

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