AT25QL641 datasheet(11/77 Pages) DIALOG

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AT25QL641

DS-25QL641–130E–10/2018

Status Registers

The Read Status Register instruction can be used to provide status on the availability of the Flash memory array, if the device

is write enabled or disabled, the state of write protection, and the Quad SPI setting. The Write Status Register instruction can

be used to configure the devices write protection features and Quad SPI setting. Write access to the Status register is

controlled, in some cases, by the WP pin.

6.1

Busy

BUSY is a read-only bit (S0) that is set to a 1 state when the device is executing a Page Program, Erase, Write Status Register

or Write Security Register instruction. During this time the device will ignore further instruction except for the Read Status

Register and Erase / Program Suspend instruction (see tW, tPP, tSE, tBE1, tBE2 and tCE in Table 8-7, AC Electrical Characteristics).

When the Program, Erase, Write Status Register or Write Security Register command has completed, hardware clears the

BUSY bit (to a 0 state), indicating the device is ready for further instructions.

6.2

Write Enable Latch (WEL)

Write Enable Latch (WEL) is a read only bit in status register (S1) that is set to a 1 after executing a Write Enable instruction.

The WEL status bit is cleared to a 0 when device is write disabled. A write disable state occurs upon power-up or after any of

the following instructions: Write Disable, Page Program, Erase and Write Status Register.

6.3

Block Protect Bits (BP2, BP1, BP0)

The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits (S4, S3, and S2) that provide write protection control and

status. Block protect bits can be set using the Write Status Register Instruction (see tW in Table 8-7, AC Electrical

Characteristics). All, none or a portion of the memory array can be protected from Program and Erase commands (see Status

Register Memory Protection table). The factory default setting for the Block Protection Bits is 0, none of the array protected.

6.4

Top/Bottom Block Protect (TB)

The Top/Bottom bit (TB) is non-volatile bits (S5) that controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top (TB

= 0) or the Bottom (TB = 1) of the array as shown in the Status Register Memory Protection table. The factory default setting is

TB = 0. The TB bit can be set with the Write Status Register Instruction depending on the state of the SRP0, SRP1, and WEL

bits.

Table 6-1.

Status Register-1

SRP

SEC

BP2

BP1

BP0

WEL

BUSY

Status

Protect 0

(Non- Volatile)

Sector Protect

(Non- Volatile)

Top/Bottom

Write Protect

(Non- Volatile)

Block Protect

(Non- Volatile)

Block Protect

(Non- Volatile)

Block Protect

(Non- Volatile)

Write Enable

Latch

Erase or Write

in Progress

Table 6-2.

Status Register-2

S15

S14

S13

S12

S11

S10

SUS

CMP

(R)

SRP1

Suspend

Status

Complement

Protect

(Non-Volatile)

Reserved

Quad Enable

(Non-Volatile)

Protect 1

(Non-Volatile)

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