CC1010-RTY1 datasheet(15/152 Pages) TI

15 / 152 page

CC1010

SWRS047

Page 15 of 152

Pin name

Alternate

function

Pin type

Description

P0.2

MI (I)

SO (O)

Digital high-Z I/O

8051 port 0, bit 2 or SPI interface master

input or Flash programming SPI slave serial

data output

P0.3

Digital high-Z I/O

8051 port 0, bit 3

P1.5

Digital high-Z I/O

8051 port 1, bit 5

P1.6

Digital high-Z I/O

8051 port 1, bit 6

P1.7

Digital high-Z I/O

8051 port 1, bit 7

P2.6

Digital high-Z I/O

8051 port 2, bit 6

P2.7

Digital high-Z I/O

8051 port 2, bit 7

PROG

Digital input

Flash program enable pad, active low

RESET

Digital input (pull-up) System reset pin, active low

DVDD

Power (D)

Digital power supply

AD0

Analog input

ADC input channel 0

AD1

Analog input

ADC input channel 1

AD2

RSSI (O),

IF (O)

Analog input/output

ADC input channel 2, RSSI (Receiver signal

strength indicator) output, or IF output when

using external demodulator

AGND

Power (A)

Analog ground connection ADC

A = Analog, D = Digital, I = input, O= Output

13. Pin description

AVDD, DVDD

Supply voltages for analog and digital

modules respectively. All supply pins

should be decoupled by capacitors. In

particular, the digital and analog supply

domains should be properly decoupled

from each other (a ferrite bead can be

used to prevent high-frequency noise from

coupling from one supply domain to

another). The placement and size of

decoupling capacitors and supply filtering

are critical with respect to LO leakage and

sensitivity. Chipcon’s reference layout

designs should be used (available from

Chipcon’s website). See also page 133 for

layout recommendations.

AGND, DGND

Ground for analog and digital modules

respectively.

Normally

one

common

ground plane is recommended. If two

separate analog and digital grounds are

used they should be interconnected in one

place, and one place only.

RFIN

This is the RF input, internally connected

to the low noise amplifier (LNA). The

signal

source

(antenna)

should

matched to the input impedance. A DC

ground is needed for LNA biasing.

RFOUT

This is the RF output, internally connected

to the power amplifier (PA). The external

load (antenna) should be matched to the

output

impedance

(optimum

load

impedance). This pin must be DC coupled

to AVDD for PA biasing (open drain

output).

L1, L2

Connection to internal voltage controlled

oscillator (VCO). An inductor should be

connected between these pins. The

inductor value will determine the VCO

tuning range. The inductor should be place

very close to the pins in order to minimize

paracitic inductance.

CHP_OUT

Charge Pump output. If the RF transceiver

is configured for external loop filter this is

the current output from the charge pump.

Normally the internal loop filter should be

used and this pin should be left open (not

connected).

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