LAN9252VSLASHML datasheet(38/329 Pages) MICROCHIP

38 / 329 page

LAN9252

DS00001909A-page 38

 2015 Microchip Technology Inc.

6.2

Resets

The device provides multiple hardware and software reset sources, which allow varying levels of the device to be reset.

All resets can be categorized into three reset types as described in the following sections:

• Chip-Level Resets

- Power-On Reset (POR)

- RST# Pin Reset

- EtherCAT System Reset

• Multi-Module Resets

- DIGITAL RESET (DIGITAL_RST)

• Single-Module Resets

- Port A PHY Reset

- Port B PHY Reset

- EtherCAT Controller Reset

The device supports the use of configuration straps to allow automatic custom configurations of various device param-

eters. These configuration strap values are set upon de-assertion of all chip-level resets and can be used to easily set

the default parameters of the chip at power-on or pin (RST#) reset. Refer to Section 6.3, "Power Management," on

page 43 for detailed information on the usage of these straps.

Table 6-1 summarizes the effect of the various reset sources on the device. Refer to the following sections for detailed

information on each of these reset types.

TABLE 6-1:

RESET SOURCES AND AFFECTED DEVICE FUNCTIONALITY

Module/

Functionality

POR

RST#

EtherCAT

System Reset

Digital

Reset

EtherCAT

Module Reset

25 MHz Oscillator

(1)

Voltage Regulators

(2)

EtherCAT Core

XXXX

PHY A

PHY B

PHY Common

(3)

Voltage Supervision

(3)

PLL

(3)

SPI/SQI Slave

XXX

Host Bus Interface

XXX

Power Management

XXX

General Purpose Timer

XXX

Free Running Counter

XXX

System CSR

XXX

Config. Straps Latched

YES

NO(4)

EEPROM Loader Run

YES

Tristate Output Pins(

YES

RST# Pin Driven Low

YES

Note

POR is performed by the XTAL voltage regulator, not at the system level

POR is performed internal to the voltage regulators

POR is performed internal to the PHY

Strap inputs are not re-latched

Only those output pins that are used for straps

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