LAN9252VSLASHML datasheet(94/329 Pages) MICROCHIP

94 / 329 page

LAN9252

DS00001909A-page 94

 2015 Microchip Technology Inc.

16-BIT WRITE

One of the Index Registers is set as described above. The address is then set to access the corresponding Data Reg-

ister. Data on D[15:0] is written on the trailing edge of WR. The cycle repeats for the upper WORD of the Data Register.

16-BIT READS AND WRITES TO CONSTANT INTERNAL ADDRESS

One of the Index Registers is set as described above. A mix of reads and writes on D[15:0] follows, with each read or

write consisting of an access to both the lower and upper WORDs of the corresponding Data Register.

FIGURE 9-30:

INDEXED ADDRESSING INTERNAL REGISTER DATA ACCESS - 16-BIT WRITE

FIGURE 9-31:

INDEXED ADDRESSING INTERNAL REGISTER DATA ACCESS - 16-BIT READS/

WRITES CONSTANT ADDRESS

INDEX,1'b0

Index 15:8

D[15:8]

A[4:1]

INDEX,1'b1

8'hXX

Index 7:0

D[7:0]

8'hXX

DATA,1'b0

Data 15:8

Data 7:0

DATA,1'b1

Data 31:24

Data 23:16

INDEX,1'b0

Index 15:8

D[15:8]

A[4:1]

INDEX,1'b1

8'hXX

Index 7:0

D[7:0]

8'hXX

DATA,1'b0

Data 15:8

Data 7:0

DATA,1'b1

Data 31:24

Data 23:16

DATA,1'b0

Data 15:8

Data 7:0

DATA,1'b1

Data 31:24

Data 23:16

DATA,1'b0

Data 15:8

Data 7:0

DATA,1'b1

Data 31:24

Data 23:16

DATA,1'b0

Data 15:8

Data 7:0

DATA,1'b1

Data 31:24

Data 23:16

DATA,1'b0

Data 15:8

Data 7:0

DATA,1'b1

Data 31:24

Data 23:16

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