LAN9252VSLASHML datasheet(81/329 Pages) MICROCHIP

81 / 329 page

 2015 Microchip Technology Inc.

DS00001909A-page 81

LAN9252

Note 7:

Dual Phase Addressing

Note 8:

Depends on ALEHI / ALELO order.

Note 9: ALELO and/or ALEHI qualified with the CS.

Note 10: RD_WR and ENB signaling.

Note 11:

No interposed address phase.

Note 12: RD and WR signaling.

TABLE 9-2:

MULTIPLEXED ADDRESSING WRITE CYCLE TIMING VALUES

Symbol

Description

Min

Typ

Max

Units

tcsale

CS Setup to ALELO, ALEHI Active

Note 9, Note 8

0ns

tcswr

CS Setup to WR or ENB Active

twrcs

CS Hold from WR or ENB Inactive

twale

ALELO, ALEHI Pulse Width

tadrs

Address Setup to ALELO, ALEHI Inactive

tadrh

Address Hold from ALELO, ALEHI Inactive

taleale

ALELO Inactive to ALEHI Active

ALEHI Inactive to ALELO Active

Note 7, Note 8

0ns

talewr

ALELO, ALEHI Inactive to WR or ENB Active

Note 8

5ns

trdwrs

RD_WR Setup to ENB Active

Note 10

5ns

trdwrh

RD_WR Hold from ENB Inactive

Note 10

5ns

tds

Data Setup to WR or ENB Inactive

tdh

Data Hold from WR or ENB Inactive

twr

WR or ENB Active Time

twrcyc

WR or ENB Cycle Time

twrale

WR or ENB De-assertion Time before Address Phase

twrwr

WR or ENB De-assertion Time before Next WR or ENB

Note 11

twrrd

WR De-assertion Time before Next RD

Note 11, Note 12

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