LAN9252VSLASHML datasheet(51/329 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001909A-page 51

LAN9252

7.0

CONFIGURATION STRAPS

Configuration straps allow various features of the device to be automatically configured to user defined values. Hard-

straps are latched upon Power-On Reset (POR), EtherCAT reset, or pin reset (RST#).

Configuration straps include internal resistors in order to prevent the signal from floating when unconnected. If a partic-

ular configuration strap is connected to a load, an external pull-up or pull-down resistor should be used to augment the

internal resistor to ensure that it reaches the required voltage level prior to latching. The internal resistor can also be

overridden by the addition of an external resistor.

7.1

Hard-Straps

Hard-straps are latched upon Power-On Reset (POR), EtherCAT reset, or pin reset (RST#) only. These straps are used

as either direct configuration values or as register defaults. Table 7-1 provides a list of all hard-straps and their associ-

ated pin. These straps, along with their pin assignments are also fully defined in Section 3.0, "Pin Descriptions and Con-

figuration," on page 11.

Note:

The system designer must guarantee that configuration strap pins meet the timing requirements specified

in Section 18.6.3, "Reset and Configuration Strap Timing". If configuration strap pins are not at the correct

voltage level prior to being latched, the device may capture incorrect strap values.

TABLE 7-1:

HARD-STRAP CONFIGURATION STRAP DEFINITIONS

Strap Name

Description

Pins

eeprom_size_strap

EEPROM Size Strap:

Configures the EEPROM size range.

A low selects 1K bits (128 x 8) through 16K bits (2K x 8).

A high selects 32K bits (4K x 8) through 4Mbits (512K x 8).

E2PSIZE

chip_mode_strap[1:0]

EtherCAT Chip Mode Strap:

This strap determines the

number of active ports and port types.

00 = 2 port mode. Ports 0 and 1 are connected to inter-

nal PHYs A and B.

01 = reserved

10 = 3 port downstream mode. Ports 0 and 1 are con-

nected to internal PHYs A and B. Port 2 is connected to

the external MII pins.

11 = 3 port upstream mode. Ports 2 and 1 are connected

to internal PHYs A and B. Port 0 is connected to the

external MII pins.

CHIP_MODE1,

CHIP_MODE0

link_pol_strap_mii

EtherCAT MII Port Link Polarity Strap:

This strap deter-

mines the polarity of the MII_LINK pin.

0 = MII_LINK low means a 100 Mbit/s Full Duplex link is

established

1= MII_LINK high means a 100 Mbit/s Full Duplex link is

established

MII_LINKPOL

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