LAN9252VSLASHML datasheet(75/329 Pages) MICROCHIP

75 / 329 page

 2015 Microchip Technology Inc.

DS00001909A-page 75

LAN9252

16-BIT READS AND WRITES TO CONSTANT ADDRESS

The address is latched simultaneously from AD[7:0] and AD[15:8]. A mix of reads and writes on AD[15:0] follows.

8-BIT READ

The address is latched simultaneously from AD[7:0] and AD[15:8]. A read on AD[7:0] follows. AD[15:8] pins are not

used or driven for the data phase as the host could potentially continue to drive the upper address on these signals. The

cycle is repeated for the other BYTEs of the DWORD.

Note:

Generally, two 16-bit reads to opposite WORDs of the same DWORD are required. 16-bit reads and writes

to the same WORD is a special case.

FIGURE 9-15:

MULTIPLEXED ADDRESSING WITH SINGLE PHASE LATCHING - 16-BIT READS

AND WRITES CONSTANT ADDRESS

FIGURE 9-16:

MULTIPLEXED ADDRESSING WITH SINGLE PHASE LATCHING - 8-BIT READ

ALELO

ALEHI

Address Low

Address High

Data 15:8

Data 7:0

Optional

AD[15:8]

AD[7:0]

Data 15:8

Data 7:0

Data 15:8

Data 7:0

Data 15:8

Data 7:0

Data 15:8

Data 7:0

ALELO

ALEHI

Address Low

Data 7:0

Address+1 Low

Data 15:8

Address High

Optional

Address+2 Low

Data 23:16

Address High

Address+3 Low

Data 31:24

Address High

Optional

AD[15:8]

AD[7:0]

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