LAN9252VSLASHML datasheet(80/329 Pages) MICROCHIP

Teilenummer	LAN9252V/ML

Bauteilbeschribung	2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs

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LAN9252

DS00001909A-page 80

 2015 Microchip Technology Inc.

Note 3: ALELO and/or ALEHI qualified with the CS.

Note 4: RD_WR and ENB signaling.

Note 5:

No interposed address phase.

Note 6: RD and WR signaling.

Note:

Timing values are with respect to an equivalent test load of 25 pF.

9.4.5.2

Write Timing Requirements

If RD and WR signaling is used, a host write cycle begins when WR is asserted with CS active. The cycle ends when

WR is de-asserted. CS maybe asserted and de-asserted along with WR but not during WR active.

Alternatively, if RD_WR and ENB signaling is used, a host write cycle begins when ENB is asserted with CS active and

RD_WR indicating a write. The cycle ends when ENB is de-asserted. CS maybe asserted and de-asserted along with

ENB but not during ENB active.

Please refer to Section 9.4.4, "Multiplexed Addressing Mode Functional Timing Diagrams," on page 68 for functional

descriptions.

FIGURE 9-22:

MULTIPLEXED ADDRESSING WRITE CYCLE TIMING

ALEHI

AD[7:0] input

ALELO

AD[15:8] input

ENB, WR

tadrs

tadrh

tcsale

talewr

twr

twale

twrwr

twrrd

twrale

twrcyc

RD_WR

trdwrs

trdwrh

tcswr

twrcs

tds

tdh

taleale

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