LAN9252VSLASHML datasheet(87/329 Pages) MICROCHIP

87 / 329 page

 2015 Microchip Technology Inc.

DS00001909A-page 87

LAN9252

8 AND 16-BIT ACCESS

For certain register accesses, the host is required to perform two or four consecutive 16 or 8-bit reads to complete a

single DWORD transfer. No ordering requirements exist. The host can access either the low or high WORD or BYTE

first, as long as the other read(s) is(are) performed from the remaining WORD or BYTEs.

A read BYTE / WORD counter keeps track of the number of reads. Each Data Register has its own BYTE / WORD

counter. These counters are separate from the write counters above. At the trailing edge of the read cycle, the appro-

priate counter (based on the captured host address from above) is incremented. On the last read for the DWORD, an

internal read is performed to update any Change on Read CSRs.

All of the read BYTE / WORD counters are reset if the power management mode is set to anything other than D0.

SPECIAL CSR HANDLING

Live Bits

Any register bit that is updated by a H/W event is held at the beginning of the read cycle to prevent it from changing

during the read cycle.

Multiple BYTE / WORD Live Registers in 16 or 8-Bit Modes

Some internal registers have fields or related fields that span across multiple BYTEs or WORDs. For 16 and 8-bit data

reads, it is possible that the value of these fields change between host read cycles. In order to prevent reading interme-

diate values, these registers are locked when the first byte or word is read and unlocked when the last byte or word is

read.

The registers are unlocked if the power management mode is set to anything other than D0.

Change on Read Registers and FIFOs

FIFOs or “Change on Read” registers, are updated at the end of the read cycle.

For 16 and 8-bit modes, only one internal read cycle is indicated and occurs for the last byte or word.

Change on Read Live Register Bits

As described above, registers with live bits are held starting at the beginning of the read cycle and those that have mul-

tiple bits that span across BYTES or WORDS are also locked for 16 and 8-bit accesses. Although a H/W event that

occurs during the hold or lock time would still update the live bit(s), the live bit(s) will be affected (cleared, etc.) at the

end of the read cycle and the H/W event would be lost.

In order to prevent this, the individual CSRs defer the H/W event update until after the read or multiple reads.

Registers Polling During Reset or Initialization

Some registers support polling during reset or device initialization to determine when the device is accessible. For these

registers, only one read may be performed without the need to read the other WORD or BYTEs. The same BYTE or

WORD of the register may be re-read repeatedly.

A register that is 16 or 8-bit readable or readable during reset or device initialization, is noted in its register description.

9.5.4.3

Host Endianness

The device supports big and little endian host byte ordering based upon the endianness bits in the Host Bus Interface

Configuration Register. When the appropriate endianness bit is low, host access is little endian and when high, host

access is big endian. Endianness is specified for each Index / Data pair and for FIFO Direct Select accesses.

All internal busses are 32-bit with little endian byte ordering. Logic within the Host Bus Interface re-orders bytes based

on the appropriate endianness bit, and the state of the least significant address lines (ADDR[1:0]).

Note:

Reading the same WORD or BYTEs from the same DWORD may cause undefined or undesirable opera-

tion. The HBI hardware does not protect against this operation. The HBI simply counts that four BYTEs

have been read.

Accessing the same internal register using two Index / Data register pairs may cause undefined or unde-

sirable operation. The HBI hardware does not protect against this operation.

Mixing reads and writes into the same Data register may cause undefined or undesirable operation. The

HBI hardware does not protect against this operation.

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