OPA607 datasheet(35/52 Pages) TI2

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4. Connections to other wideband devices on the board can be made with short direct traces or through

onboard transmission lines. For short connections, consider the trace and the input to the next device as a

lumped capacitive load. Relatively wide traces (50 mils to 100 mils) must be used, preferably with ground

and power planes opened up around them. Estimate the total capacitive load and set RS for sufficient phase

margin and stability. Low parasitic capacitive loads (< 10 pF) do not always require an RS because the

OPA810 is nominally compensated to operate with a 10-pF parasitic load. Higher parasitic capacitive loads

without an RS are allowed with increase in signal gain (increasing the unloaded phase margin). If a long

trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable,

implement a matched impedance transmission line using microstrip or stripline techniques (consult an

ECL design handbook for microstrip and stripline layout techniques). A 50-Ω environment is normally not

necessary onboard, and a higher impedance environment improves distortion. With a characteristic board

trace impedance defined based on board material and trace dimensions, a matching series resistor into

the trace from the output of the OPA810 is used as well as a terminating shunt resistor at the input of the

destination device. Remember also that the terminating impedance is the parallel combination of the shunt

resistor and the input impedance of the destination device—this total effective impedance must be set to

match the trace impedance. If the 6-dB attenuation of a doubly-terminated transmission line is unacceptable,

a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case

and set the series resistor value to obtain sufficient phase margin and stability. This does not preserve signal

integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, the

signal attenuates because of the voltage divider formed by the series output into the terminating impedance.

5. Take care to design the PCB layout for optimized thermal dissipation. For the extreme case of 125°C

operating ambient, using the approximate 134.8°C/W for the SOIC package, and an internal power of

24-V supply × 4.7-mA 125°C supply current gives a maximum internal power dissipation of 113 mW. This

power gives a 15°C increase from ambient to junction temperature. Load power adds to this value and this

dissipation must also be calculated to determine the worst-case safe operating point.

6. Socketing a high-speed device such as the OPA810 is not recommended. The additional lead length

and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network

that can almost make achieving a smooth, stable frequency response impossible. Best results are obtained

by soldering the OPA810 onto the board.

8.4.1.1 Thermal Considerations

The OPA810 does not require a heat sink or airflow in most applications. Maximum allowed junction temperature

sets the maximum allowed internal power dissipation. Do not allow the maximum junction temperature to exceed

150°C.

Operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the

sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power.

Quiescent power is the specified no-load supply current times the total supply voltage across the part. PDL

depends on the required output signal and load, but for a grounded resistive load, is at a maximum when the

output is fixed at a voltage equal to half of either supply voltage (for equal split-supplies). Under this condition,

PDL = VS 2 / (4 × RL) where RL includes feedback network loading.

The power in the output stage and not into the load that determines internal power dissipation.

As a worst-case example, compute the maximum TJ using a DCK (SC70 package) configured as a unity gain

buffer, operating on ±12-V supplies at an ambient temperature of 25°C and driving a grounded 500-Ω load.

PD = 24 V × 4.7 mA + 122 / (4 × 500 Ω) = 184.8 mW

Maximum TJ = 25°C + (0.185 W × 190.8°C/W) = 60°C, which is much less than the maximum allowed junction

temperature of 150°C.

www.ti.com

OPA810

SBOS799E – AUGUST 2019 – REVISED AUGUST 2024

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