6.7 Electrical Characteristics: 5 V (continued)

at TA = 25°C, VS+ = 5 V, VS– = 0 V, common-mode voltage (VCM) = 1.25 V, and RL = 1 kΩ connected to 1.25 V(1) (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Test

Level(2)

Most positive input voltage

ΔVOS < 5 mV(4)

VS+ + 0.2

VS+ + 0.3

V

A

Most negative input voltage

ΔVOS < 5 mV(4)

VS- – 0.2

VS- – 0.3

V

A

Most positive input voltage

for main-JFET stage

See Figure 6-41

VS+ – 2.9

VS+ – 2.5

V

C

OUTPUT

VOCRH

Output voltage range high

RL = 667 Ω

VS+ – 0.12 VS+ – 0.09

V

A

TA = –40°C to +125°C, RLOAD = 667 Ω

VS+ – 0.15

B

VOCRL

Output voltage range low

RL = 667 Ω

VS–+ 0.06

VS– +

0.11

V

A

TA = –40°C to +125°C, RL = 667 Ω

VS– +

0.15

B

IO(max)

Linear output drive (sourcing

and sinking)

VO = 1.4 V, RL = 27.5 Ω, ΔVOS < 1

mV, VS+ = 3 V and VS– = –2 V

50

64

mA

A

ISC

Output short-circuit current

96

mA

B

CL

Capacitive load drive

< 3-dB peaking, RS = 0 Ω

10

pF

C

POWER SUPPLY

IQ

Quiescent current per

channel

3.15

3.7

4.5

mA

A

PSRR

Power-supply rejection ratio

ΔVS = ±0.5 V(5), SOIC package

78

100

dB

A

TA = –40°C to +125°C, SOIC package

78

B

AUXILIARY CMOS INPUT STAGE

Gain-bandwidth product

27

MHz

C

Input-referred voltage noise

f = 1 MHz

20

nV/√Hz

C

Input offset voltage

VCM = VS+ – 1.5 V, no load, SOIC

package

1.6

mV

A

Input bias current

VCM = VS+ – 1.5 V

2

20

pA

A

(1)

For ac specifications, VS+ = 3.5 V, VS– = –1.5 V, G = 2 V/V, RF = 1 kΩ, CL = 4.7 pF, VCM = 0 V (unless otherwise noted).

(2)

Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and

simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.

(3)

Lower of the measured positive and negative slew rate.

(4)

Change in input offset from the value when input is biased to 0 V.

(5)

Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to

+PSRR and –PSRR.

OPA810

SBOS799E – AUGUST 2019 – REVISED AUGUST 2024

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