ADP1876

Data Sheet

Rev. A | Page 8 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

EN1

Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 controller, and drive it low to turn it off. Tie EN1

to VIN for automatic startup. For a precision UVLO, put an appropriately sized resistor divider from VIN to AGND and

tie the midpoint to this pin.

2

VIN

Connect to Main Power Supply. Bypass with a 1 μF or larger ceramic capacitor connected as close to this pin as

possible and PGNDx.

3

VINLDO

Input for Independent Linear Dropout (LDO) Regulator.

4

VOUTLDO

Output for Independent LDO Regulator.

5

VCCO

Output of the Internal LDO. The internal circuitry and gate drivers are powered from VCCO. Bypass VCCO to AGND

with a 1 μF or larger ceramic capacitor. The VCCO output is always active, even during fault conditions, and it

cannot be turned off even when EN1 or EN2 is low. For operation at VIN below 5 V, VIN can be jumped to VCCO. Do

not use the VCCO to power any other auxiliary system load.

6

VDL

Power Supply for the Low-Side Driver. Bypass VDL to PGNDx with a 1 μF ceramic capacitor. Connect VCCO to VDL.

7

AGND

Analog Ground.

8

NC

No connect. Do not connect to this pin.

9

EN2

Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 controller, and drive it low to turn off. Tie EN2

to VIN for automatic startup. For a precision UVLO, put an appropriately sized resistor divider from VIN to AGND and

tie the midpoint to this pin.

10

FB2

Output Voltage Feedback for Channel 2.

11

COMP2

Compensation Node for Channel 2. Output of the Channel 2 error amplifier. Connect a series resistor/capacitor

network from COMP2 to AGND to compensate the regulation control loop.

12

RAMP2

Programmable Current Setting for Slope Compensation of Channel 2. Connect a resistor from RAMP2 to VIN. The

voltage at RAMP2 is 0.2 V during operation. This pin is high impedance when the channel is disabled.

13

SS2

Soft Start Input for Channel 2. Connect a capacitor from SS2 to AGND to set the soft start period. This node is

internally pulled up to 3.2 V through a 6.5 µA current source.

14

PGOOD2

Open-Drain Power-Good Indicator Logic Output at PGOOD2. An internal 12 kΩ resistor is connected between

PGOOD2 and VCCO. PGOOD2 is pulled to ground when the Channel 2 output is outside the regulation window. An

external pull-up resistor is not required.

15

ILIM2

Current-Limit Sense Comparator Inverting Input for Channel 2. Connect a resistor between ILIM2 and SW2 to set

the current-limit offset. For accurate current-limit sensing, connect ILIM2 to a current sense resistor at the source of

the low-side MOSFET.

16

BST2

Boot Strapped Upper Rail of High-Side Internal Driver for Channel 2. Connect a 0.1 µF to 0.22 µF multilayer ceramic

capacitor (MLCC) between BST2 and SW2. There is an internal boost rectifier connected between VDL and BST2.

24 SW1

23 DH1

22 PGND1

21 DL1

20 DL2

19 PGND2

18 DH2

17 SW2

1

2

3

4

5

6

7

8

EN1

VIN

VINLDO

VOUTLDO

VCCO

VDL

AGND

NC

ADP1876

TOP VIEW

(Not to Scale)

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. CONNECT THE BOTTOM EXPOSED PAD OF THE

LFCSP PACKAGE TO SYSTEM AGND PLANE.