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ADP1876ACPZ-R7 Datenblatt(PDF) 20 Page - Analog Devices |
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ADP1876ACPZ-R7 Datenblatt(HTML) 20 Page - Analog Devices |
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20 / 24 page ![]() ADP1876 Data Sheet Rev. A | Page 20 of 24 Usually, the impedance is dominated by ESR, such as in electrolytic or polymer capacitors, at the switching frequency, as stated in the maximum ESR rating on the capacitor data sheet; therefore, output ripple reduces to ESR L OUT R I V × ∆ ≅ ∆ Electrolytic capacitors also have significant ESL, on the order of 5 nH to 20 nH, depending on type, size, and geometry. PCB traces contribute some ESR and ESL, as well. However, using the maximum ESR rating from the capacitor data sheet often provides enough margin such that measuring the ESL is not usually required. In the case of output capacitors where the impedance of the ESR and ESL are small at the switching frequency, for instance, where the output capacitor is a bank of parallel MLCC capacitors, the capacitive impedance dominates and the output capacitance equation reduces to SW OUT L OUT f V I C × ∆ ∆ ≅ 8 Ensure that the ripple current rating of the output capacitors is greater than the maximum inductor ripple current. For example, during a load step transient on the output, when the load is suddenly increased, the output capacitor supplies the load until the control loop has a chance to ramp the inductor current. This initial output voltage deviation results in a voltage droop or undershoot. The output capacitance (assuming 0 Ω ESR) that is required to satisfy the voltage droop requirement can be approximated by SW DROOP STEP OUT f V I C × ∆ ∆ ≅ where: ∆ISTEP is the step load. ∆VDROOP is the voltage droop at the output. When a load is suddenly removed from the output, the energy stored in the inductor rushes into the capacitor, causing the output to overshoot. The output capacitance required to satisfy the output overshoot requirement can be approximated by 2 2 2 ) ( OUT OVERSHOOT OUT STEP OUT V V V L I C − ∆ + ∆ ≅ where: ∆VOVERSHOOT is the overshoot voltage during the step load. Select the largest output capacitance given by any of the previous three equations. MOSFET SELECTION The choice of MOSFET directly affects the dc-to-dc converter performance. A MOSFET with low on resistance reduces I2R losses, and a low gate charge reduces transition losses. A MOSFET that has low thermal resistance ensures that the power dissipated in the MOSFET does not result in excessive MOSFET die tem- perature. The high-side MOSFET carries the load current during on time and usually carries most of the transition losses of the converter. Typically, the lower the on resistance of the MOSFET, the higher the gate charge, and vice versa. Therefore, it is important to choose a high-side MOSFET that balances the two losses. The conduction loss of the high-side MOSFET is determined by the equation × ≅ IN OUT DSON LOAD C V V R I P 2 ) ( where: RDSON is the MOSFET on resistance. The gate charging loss is approximated by the equation PG ≅ VPV × QG × fSW where VPV is the gate driver supply voltage. QG is the MOSFET total gate charge. Note that the gate charging power loss is not dissipated in the MOSFET but rather in the ADP1876 internal drivers. This power loss must be considered when calculating the overall power efficiency. The high-side MOSFET transition loss is approximated by the equation 2 ) ( SW F R LOAD IN T f t t I V P × + × × ≅ where: PT is the high-side MOSFET switching loss power. tR is the rise time in charging the high-side MOSFET. tF is the fall time in discharging the high-side MOSFET. tR and tF can be estimated by the following equations: RISE DRIVER GSW R I Q t _ ≅ FALL DRIVER GSW F I Q t _ ≅ where: QGSW is the gate charge of the MOSFET during switching and is given in the MOSFET data sheet. IDRIVER_RISE and IDRIVER_FALL are the driver current output by the ADP1876 internal gate drivers. If QGSW is not given in the data sheet, it can be approximated by 2 GS GD GSW Q Q Q + ≅ where QGD and QGS are the gate-to-drain and gate-to-source charges given in the MOSFET data sheet. IDRIVER_RISE and IDRIVER_FALL can be estimated by GATE SOURCE ON SP DD RISE DRIVER R R V V I + − ≅ _ _ |
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