Data Sheet

ADP1876

Rev. A | Page 9 of 24

Pin No.

Mnemonic

Description

17

SW2

Switch Node for Channel 2. Connect to the source of the high-side N-channel MOSFET and the drain of the low-

side N-channel MOSFET of Channel 2.

18

DH2

High-Side Switch Gate Driver Output for Channel 2.

19

PGND2

Power Ground for Channel 2. Ground for Internal Channel 2 driver. Differential current is sensed between SW2 and

PGND2. Directly shorting PGND2 to PGND1 is not recommended.

20

DL2

Low-Side Synchronous Rectifier Gate Driver Output for Channel 2. To set the gain of the current sense amplifier,

connect a resistor between DL2 and PGND2.

21

DL1

Low-Side Synchronous Rectifier Gate Driver Output for Channel 1. To set the gain of the current sense amplifier,

connect a resistor between DL1 and PGND1.

22

PGND1

Power Ground for Channel 1. Ground for internal Channel 1 driver. Differential current is sensed between SW1 and

PGND1. Directly shorting PGND2 to PGND1 is not recommended.

23

DH1

High-Side Switch Gate Driver Output for Channel 1.

24

SW1

Power Switch Node for Channel 1. Connect SW1 to the source of the high-side N-channel MOSFET and the drain of

the low-side N-channel MOSFET of Channel 1.

25

BST1

Boot Strapped Upper Rail of High-Side Internal Driver for Channel 1. Connect a 0.1µF to 0.22 µF multilayer ceramic

capacitor (MLCC) between BST1 and SW1. There is an internal boost diode or rectifier connected between VDL

and BST1.

26

ILIM1

Current-Limit Sense Comparator Inverting Input for Channel 1. Connect a resistor between ILIM1 and SW1 to set

the current-limit offset. For accurate current-limit sensing, connect ILIM1 to a current sense resistor at the source of

the low-side MOSFET.

27

PGOOD1

Open-Drain Power-good Indicator Logic Output. PGOOD1 includes an internal 12 kΩ resistor connected between

PGOOD1 and VCCO. PGOOD1 is pulled to ground when the Channel 1 output is outside the regulation window. An

external pull-up resistor is not required.

28

SS1

Soft Start Input for Channel 1. Connect a capacitor from SS1 to AGND to set the soft start period. This node is

internally pulled up to 3.2 V through a 6.5 µA current source.

29

RAMP1

Programmable Current Setting for Channel 1 Slope Compensation. Connect a resistor from RAMP1 to VIN. The

voltage at RAMP1 is 0.2 V during operation. This pin is high impedance when the channel is disabled.

30

COMP1

Compensation Node For Channel 1. Output of Channel 1 error amplifier. Connect a series resistor/capacitor

network from COMP1 to AGND to compensate the regulation control loop.

31

FB1

Output Voltage Feedback for Channel 1.

32

TRK1

Tracking Input for Channel 1.