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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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P83C266BDR Datenblatt(PDF) 35 Page - NXP Semiconductors |
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P83C266BDR Datenblatt(HTML) 35 Page - NXP Semiconductors |
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35 / 92 page  1999 Mar 10 35 Philips Semiconductors Product specification Microcontrollers for PAL/SECAM TV with OSD and VST P8xCx66 family 15 ANALOG CONTROL The P8xCx66 has nine Pulse Width Modulated (PWM) outputs for analog control purposes e.g., volume, balance, brightness, voltage synthesized tuning etc. Each PWM output generates a pulse pattern with a programmable duty cycle. The nine PWM outputs are specified below: • 8 PWM outputs with 7-bit resolution (PWM0 to PWM7) • 1 PWM output with 14-bit resolution (TPWM). The 7-bit PWM outputs are described in Section 15.1 and the 14-bit PWM output is described in Section 15.2. 15.1 7-bit PWM outputs (PWM0 to PWM7) The block diagram of a typical 7-bit PWM circuit is shown in Fig.19. PWM outputs PWM0 to PWM7 share the same pins as general I/O port lines P5.1 to P5.7 and P3.3 respectively. Selection of the pin function as either a PWM output or general I/O port line is achieved by setting the PWMnE bit in the associated PWM register (where n = 0 to 7). The PWM registers are shown in Table 38. The clock frequency of each PWM circuit is 1 ⁄4fosc and therefore the repetition frequency of each 7-bit PWM output is 1 ⁄512fosc. The polarity of each PWM output is fixed active HIGH. The HIGH period of each PWM output is dependent upon the contents of the PWM data latch and may be calculated as shown below: where (PWMn) is the decimal value held in the PWMn data latch The PWM output analog value is determined by the ratio of the HIGH period and the repetition period. A DC voltage proportional to the PWM control setting is obtained by means of an external integration network (low-pass filter) connected to the PWM output pin. The rising edge of each of the 8 PWM outputs is separated by one 1 ⁄4fosc cycle, this is shown in Fig.21. PWM1 will always start at ‘2’, and PWM5 will start at ‘6’ independent of other PWMs value. Figure 20 shows active HIGH PWM output patterns. t HIGH 4 PWMn () × f osc ---------------------------------- = Table 38 7-bit PWM data registers REGISTER ADDRESS 76543210 PWM0 E4H PWM0E data6 data5 data4 data3 data2 data1 data0 PWM1 E5H PWM1E data6 data5 data4 data3 data2 data1 data0 PWM2 E6H PWM2E data6 data5 data4 data3 data2 data1 data0 PWM3 E7H PWM3E data6 data5 data4 data3 data2 data1 data0 PWM4 ECH PWM4E data6 data5 data4 data3 data2 data1 data0 PWM5 EDH PWM5E data6 data5 data4 data3 data2 data1 data0 PWM6 EEH PWM6E data6 data5 data4 data3 data2 data1 data0 PWM7 EFH PWM7E data6 data5 data4 data3 data2 data1 data0 |
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