P83C266BDR datasheet(84/92 Pages) PHILIPS

84 / 92 page

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Notes

1. A pull-up resistor must be present to prevent a floating input during normal/alternative mode when no external signal is applied to the pad.

Pull-up = present internally.

2. All ports are in input mode after reset; that means the value at the pin is determined by the external circuitry: pull-up registers Rext (and/or external

applied input).

3. A pull-up resistor must be present to prevent floating (digital) inputs if the pad is used for the analog inputs ADCO, ADCI and ADC2. This pull-up is

also present if these pins are used as port function. Pull-up is internally.

4. These pins are standard I/O cells SPF20PGD (2 mA PP slew-rate controlled).

5. A pull-up resistor must be present to prevent a floating input during nominal/alternative mode when no external signal is applied to the pad.

Pull-up = present internally.

6. Inverse of the Bp bit (located in OSCON).

7. After reset the Bp bit (located in OSCON) = 1, therefore output becomes LOW.

8. Its pull-down resistor is present internally (see Section 13.2).

9. For the SDIP42 package, pin P1.0 can be exchanged for a VSS or VDD, pin P1.7 for a VSS.

10. For the PLCC68 package, pin P1.0 can be exchanged for a VDD line.

11. Output is HIGH via external resistor.

−

n.c.

−−

−

P1.3

I/O

TTL STr

open-drain

Yes

original state

Z(2)

INT0

TTL STr

−−

−

P1.4

I/O

TTL STr

open-drain

Yes

original state

Z(2)

TTL STr

−−

−

P1.5

I/O

TTL STr

open-drain

Yes

original state

Z(2)

SCL

I/O

TTL STr

open-drain

Yes

HIGH(11)

−

P1.6

I/O

TTL STr

open-drain

Yes

original state

Z(2)

SDA

I/O

TTL STr

open-drain

Yes

HIGH(11)

−

P1.7

I/O

TTL STr

open-drain + Rpu(5) Yes

original state

Z(2)

−

VSS

−

note 9

−−

−

VSS

−−

−

VDD

−−

−

SYMBOL

TYPE

INPUT LEVEL

OUTPUT TYPE

SLOPE

CONTROL

OUTPUT IN

IDLE MODE

OUTPUT

AFTER RESET

ACTIVE STATE

SW CONTROL

SDIP42

PLCC68

P83C266BDR Datenblatt(PDF) 84 Page - NXP Semiconductors

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