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P83C266BDR Datenblatt(PDF) 67 Page - NXP Semiconductors |
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P83C266BDR Datenblatt(HTML) 67 Page - NXP Semiconductors |
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67 / 92 page ![]() 1999 Mar 10 67 Philips Semiconductors Product specification Microcontrollers for PAL/SECAM TV with OSD and VST P8xCx66 family 17.14 OSD vertical debouncing circuit The HSYNC and VSYNC signals entering the OSD circuit are usually extracted from the horizontal and vertical deflection units of a television set. The shaping and timing of these signals is therefore related to several external conditions that all have certain tolerances. The trigger levels of the input circuitry also influence the internal timing of HSYNC and VSYNC. In the odd field the leading edge of both signals is very close, so jitter on one or both of them may result in occasionally miscounting the number of lines in a field causing a displayed character to bounce up and down on a line. To avoid this situation the HSYNC signal is delayed by a number of dot clocks. Because the relationship between HSYNC and VSYNC is not fully known there are 16 user selectable delays available. The period of the horizontal starting position plus the HDEL delay cannot exceed the HSYNC period. 17.14.1 HORIZONTAL DELAY REGISTER (HDEL) Table 76 Horizontal Delay Register (SFR address C6H) Table 77 Description of HDEL bits Table 78 Selection of HSYNC delay 76543210 −−−− HDEL3 HDEL2 HDEL1 HDEL0 BIT SYMBOL DESCRIPTION 7to4 − These 4 bits are reserved. 3 HDEL3 HSYNC delay. The state of these 4 bits determines the delay time applied to the HSYNC signal, see Table 78. 2 HDEL2 1 HDEL1 0 HDEL0 HDEL3 HDEL2 HDEL1 HDEL0 NO. OF DOT CLOCKS DELAY TIME AT 5 MHz ( µs) DELAY TIME AT 10 MHz ( µs) 00000 0 0 0001 32 6.4 3.2 0010 64 12.8 6.4 0011 96 19.2 9.6 0100 128 25.6 12.8 0101 160 32 16 0110 192 38.4 19.2 0111 224 44.8 22.4 1000 256 51.2 25.6 1001 288 57.6 28.8 1010 320 64 32 1011 352 70.4 35.2 1100 384 76.8 38.4 1101 416 83.2 41.6 1110 448 89.6 44.8 1111 480 96 48 |
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