P83C266BDR datasheet(55/92 Pages) PHILIPS

55 / 92 page

1999 Mar 10

Philips Semiconductors

Product speciﬁcation

Microcontrollers for PAL/SECAM TV

with OSD and VST

P8xCx66 family

17.5

Display RAM organization

The display character RAM is organized as 192

× 12 bits.

The general format of each RAM location is as follows.

Bits <11-5> hold character data: 1 out of 128 different

character fonts may be specified (126 customized fonts

plus 2 reserved codes). Bits <4-0> hold attribute data of

the character font, for example, colour, character size etc.

17.5.1

DISPLAY RAM FORMATS

There are four different formats to be considered:

1. Customer character code.

2. Carriage Return code

3. Space code 1 and Space code 2.

These formats are shown in Tables 70 to 72.

17.5.1.1

Customer character code

If bits <11-5> are in the range 00H to 7CH then this is a

customized character code.

Bits <4-2> select the character colour, a choice of

8 colours are available.

Bit <0> determines whether the character blinks or not.

The actual blinking frequency is determined by the BF bit

in SFR OSCON.

17.5.1.2

Carriage Return code

If bits <11-5> hold 7EH then this is the Carriage Return

code. A transparent pattern will be displayed on the

screen, the current display row will be terminated and the

character stored in the display RAM next to this code will

be displayed at the beginning of the next row.

Bits <4-3> select the size of the characters to be displayed

in the next row. The character size is independently

controlled in both the vertical and the horizontal direction.

Bit <4> controls the vertical size as shown in Table 65 and

bit <3> controls the horizontal size as shown in Table 66.

Figure 34 shows the four different character sizes

available.

Bits <2-1> select the display sub-mode of the next row.

Four sub-modes can be selected (see Table 67) in either

the Frame mode or the TV mode. Therefore a total of

8 different modes are available, these are illustrated in

Figs 35 and 36.

Bit <0> is the end of display control bit and stops the

display function before the last display RAM address

(191 decimal). By combining the ‘end of display’ feature

with the start RAM address (controlled by SFR OSSTART)

the display RAM can be configured into several banks for

fast display data switching. The states of the end of display

control bit are defined in Table 68.

Table 65 Selection of vertical size

Table 66 Selection of horizontal size

Table 67 Selection of sub-modes

Table 68 End of display control

BIT 4

VERTICAL SIZE

One vertical dot is equal to one horizontal

scan-line width.

One vertical dot is equal to two horizontal

scan-line widths.

BIT 3

HORIZONTAL SIZE

One horizontal dot is equal to one OSD clock

width.

One horizontal dot is equal to two OSD clock

widths.

BIT 2

BIT 1

SUB-MODE

Superimpose

North-West shadowing

Box shadowing

Border shadowing

BIT 0

OPERATION

Continue to display in next row.

Stop the display and wait for the next display

ﬁeld. As soon as the horizontal and vertical

starting position has been reached, continue

to display.

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