P83C266BDR datasheet(28/92 Pages) PHILIPS

28 / 92 page

1999 Mar 10

Philips Semiconductors

Product speciﬁcation

Microcontrollers for PAL/SECAM TV

with OSD and VST

P8xCx66 family

11.9

Interrupt Request Flag Register (IRQ1)

Bits IQ9 and IQ6 to IQ2 will be set to a logic 1, if one of the two conditions specified below is met:

• If its associated port line is programmed to generate an interrupt when HIGH (selected using the Interrupt Polarity

• If its associated port line is programmed to generate an interrupt when LOW (selected using the Interrupt Polarity

IQ7 is set to a logic 1, if the interrupt condition is met within the corresponding derivative function. Therefore, all IRQ1 bits

serve not only as pending interrupt request bits but also as interrupt status bits. This means that even if the external

interrupts are disabled (using the Interrupt Enable Register 1) the IRQ1 bits can still be set to a logic 1 if the interrupt

condition is met within the corresponding derivative function. For example, if the interrupt condition within VSYNC is met

then:

• If IEN0.7 = X, IEN1.5 = 0 then IRQ1.5 = 1, no pending interrupt to CPU

• If IEN0.7 = 0, IEN1.5 = 1 then IRQ1.5 = 1, interrupt to CPU is pending

• If IEN0.7 = 1, IEN1.5 = 1 then IRQ1.5 = 1, interrupt will be serviced when either:

– The CPU finishes current instruction, if not in the interrupt service routine

– The current interrupt service routine is interrupted if the VSYNC has a higher interrupt priority

– This VSYNC interrupt becomes pending, waiting until the current higher priority level interrupt is serviced.

Bits IQ9 and IQ7 to IQ2 can be reset by software.

Table 31 Interrupt Request Flag Register (SFR address C0H)

Table 32 Description of IRQ1 bits

76543210

IQ9

−

IQ7

IQ6

IQ5

IQ4

IQ3

IQ2

BIT

SYMBOL

DESCRIPTION

IQ9

external interrupt 9 request flag (P1.7 port line)

−

reserved

IQ7

external interrupt 7 request flag (VSYNC interrupt)

IQ6

external interrupt 6 request flag (P1.4 port line)

IQ5

external interrupt 5 request flag (P1.3 port line)

IQ4

external interrupt 4 request flag (P1.2 port line)

IQ3

external interrupt 3 request flag (P1.1 port line)

IQ2

external interrupt 2 request flag (P1.0 port line)

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