Datenblatt-Suchmaschine für elektronische Bauteile
  German  ▼
ALLDATASHEETDE.COM

X  

P83C266BDR Datenblatt(PDF) 44 Page - NXP Semiconductors

Teilenummer P83C266BDR
Bauteilbeschribung  80C51 8-bit CPU
PDF  92 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Hersteller  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

P83C266BDR Datenblatt(HTML) 44 Page - NXP Semiconductors

Back Button P83C266BDR Datasheet HTML 40Page - NXP Semiconductors P83C266BDR Datasheet HTML 41Page - NXP Semiconductors P83C266BDR Datasheet HTML 42Page - NXP Semiconductors P83C266BDR Datasheet HTML 43Page - NXP Semiconductors P83C266BDR Datasheet HTML 44Page - NXP Semiconductors P83C266BDR Datasheet HTML 45Page - NXP Semiconductors P83C266BDR Datasheet HTML 46Page - NXP Semiconductors P83C266BDR Datasheet HTML 47Page - NXP Semiconductors P83C266BDR Datasheet HTML 48Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 44 / 92 page
background image
1999 Mar 10
44
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
16 ANALOG-TO-DIGITAL CONVERTERS (ADC)
The 3 channel ADC consists of a 4-bit Digital-to-Analog
Converter (DAC), a comparator, an analog channel
selector and control circuitry. The block diagram of the
ADC circuit is shown in Fig.27.
One of these channels can be used to measure the level
of the Automatic Frequency Control signal. This is
achieved by comparing the ADC signal with the output of
a 4 bit DAC using the comparator (accuracy
±12 LSB).
The ADC inputs ADC0, ADC1 and ADC2 share the same
pins as general I/O port lines P3.0, P3.1 and P3.2,
respectively. Selection of the pin function as either an ADC
input or a general I/O port line is achieved using bits
ADCE0, ADCE1 and ADCE2 in SFR SAD2 (see
Section 16.2).
The conversion time of the ADC is equal to 8 machine
cycles (8
µs at 12 MHz). Some NOP instructions should be
added in between the instruction which changes the
reference voltage or the channel selection and the
instruction which reads the VHI register bit. The ST bit
must be set to a logic 1 at the same time as the reference
voltage or channel selection change, otherwise the VHI
state of the previous comparison will be read out.
The recommended procedure is as follows:
1. Write SFR SAD (X, CH<1:0>, ST = 1, SAD<3:0>)
2. Wait 8 machine cycles (for example 8 NOPs)
3. Read SFR SAD for VHI value.
ST is reset by hardware when it is set to a logic 1 by a
written instruction. When ST is read, the value is always a
logic 0.
Fig.27 ADC block diagram.
handbook, full pagewidth
4-BIT DAC
COMPARATOR
SAD3
SAD2
SAD1
SAD0
ADCE1
ADCE0
ADCE2
CH1
CH0
MGL397
ADC enable selection (SFR address: CAH)
AFC value selection (SFR address: C8H)
ENABLE
SELECTOR
ADC
CHANNEL
SELECTOR
P3.2/ADC2
P3.1/ADC1
P3.0/ADC0
Vref
EN
DERIVATIVE PORT
SELECTOR
EN1
EN0
VHI
(SFR address: C8H)
internal bus
Channel selection
EN2



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92


Datenblatt Download

Go To PDF Page


Link URL



War ALLDATASHEET hilfreich?  [ DONATE ] 

Über Alldatasheet   |   Werbung   |   Kontakt   |   Privatsphäre und Datenschutz   |   Link zum Datenblatt    |   Linktausch   |   Hersteller
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com