T25S16AFEPR datasheet(49/74 Pages) HMSEMI

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Figure 7.16 Fast Read Quad Output Instruction

7.3.5 Fast Read Dual I/O (BBh)

The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO

pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input

the Address bits (A23-0) two bits per dock. This reduced instruction overhead may allow for code execution

(XIP) directly from the Dual SPI in some applications.

Fast Read Dual I/O with "Continuous Read Mode"

The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the

"Continuous Read Mode" bits (M7-0) after the input Address bits (A23-0), as shown in Figure 7.17. The upper

nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the inclusion or

exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don't care ("X"). However,

the IO pins should be high-impedance prior to the falling edge of the first data out clock. It is recommended to

input FFFFh on IO0 for the next instruction (16 clocks), to ensure M4 = 1 and return the device to normal

operation.

Figure 7.17 Fast Read Dual I/O Instruction (Initial command or previous M5-4≠10)

Note:

1. Least significant 4 bits of Mode are don’t care and it is optional for the host to drive these bits. The host may turn off drive during these

cycles to increase bus turnaround time between Mode bits from host and returning data from the memory

Figure 7.18 Fast Read Dual I/O Instruction (Initial command or previous M5-4=10)

7.3.6 Fast Read Quad I/O (EBh)

The Fast Read Quad I/O (EBh) command is similar to the Fast Read Dual I/O (BBh) command except

that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and Dummy clock are

required prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster

random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status

HM25Q128A

T25S16AFEPR Datenblatt(PDF) 49 Page - Shenzhen Huazhimei Semiconductor Co., Ltd