T25S16AFEPR datasheet(22/74 Pages) HMSEMI

22 / 74 page

1. While a faster RESET# pulse (as short as a few hundred nanoseconds) will often reset the device, a 1us minimum is recommended to

ensure reliable operation.

6.2. Status Register

The Read and Write Status Registers commands can be used to provide status and control of the flash

memory device.

Status Register-1 (SR1) and Status Register-2 (SR2) can be used to provide status on the availability of

the flash memory array, whether the device is write enabled or disabled, the state of write protection, Quad

SPI setting, Security Register lock status, and Erase / Program Suspend status.

SR1 and SR2 contain non-volatile bits in locations SR1[7:2] and SR2[6:3], SR2[1] that control sector

protection, OTP Register Protection, Status Register Protection, and Quad mode. Bits located in SR2[7],

SR1[1], and SR1[0] are read only volatile bits for suspend, write enable, and busy status. These are updated

by the memory control logic. The SR1[1] write enable bit is set only by the Write Enable (06h) command and

cleared by the memory control logic when an embedded operation is completed.

Write access to the non-volatile Status Register bits is controlled by the state of the non-volatile Status

Status Registers command, and while Quad mode is not enabled, the WP# pin.

A volatile version of bits SR2[6], SR2[1], and SR1[7:2] that control sector protection and Quad Mode is

used to control the behavior of these features after power up. During power up or software reset, these

volatile bits are loaded from the non-volatile version of the Status Register bits. The Write Enable for Volatile

Status Register (50h) command can be used to write these volatile bits when the command is followed by a

Write Status Registers (01h/31h/11h) command. This gives more flexibility to change the system configuration

and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting

the endurance of the Status Register non-volatile bits.

Write access to the volatile SR1, SR2 and SR3 Status Register bits is controlled by the state of the

non-volatile Status Register Protect bits SR1[7] and SR2[0] (SRP0, SRP1), the Write Enable for Volatile

Status Register command (50h) preceding a Write Status Registers command, and the WP# pin while Quad

mode is not enabled.

Status Register-3 (SR3) is used to configure and provide status on the variable HOLD# or RESET#

function, Output Driver Strength, High Frequency Enable Bit, Write Protect Selection and read latency.

Write access to the volatile SR3 Status Register bits is controlled by Write Enable for Volatile Status

HM25Q128A

T25S16AFEPR Datenblatt(PDF) 22 Page - Shenzhen Huazhimei Semiconductor Co., Ltd