T25S16AFEPR datasheet(20/74 Pages) HMSEMI

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6. FUNCTION DESCRIPTION

6.1 SPI Operations

6.1.1 SPI Modes

The

HM25Q128A

can be driven by an embedded microcontroller (bus master) in either of the two

following clocking modes.



Mode 0 with Clock Polarity (CPOL) = 0 and, Clock Phase (CPHA) = 0



Mode 3 with CPOL = 1 and, CPHA = 1

For these two modes, input data is always latched in on the rising edge of the CLK signal and the output

data is always available on the falling edge of the CLK clock signal.

The difference between the two modes is the clock polarity when the bus master is in standby mode and

not transferring any data.



CLK will stay at logic low state with CPOL = 0, CPHA = 0



CLK will stay at logic high state with CPOL = 1, CPHA = 1

Figure 6.1 SPI Modes

Timing diagrams throughout the rest of the document are generally shown as both mode 0 and 3 by

showing CLK as both high and low at the fall of CS#. In some cases a timing diagram may show only mode 0

with CLK low at the fall of CS#. In such case, mode 3 timing simply means clock is high at the fall of CS# so

no CLK rising edge set up or hold time to the falling edge of CS# is needed for mode 3.

CLK cycles are measured (counted) from one falling edge of CLK to the next falling edge of CLK. In

mode 0 the beginning of the first CLK cycle in a command is measured from the falling edge of CS# to the first

falling edge of CLK because CLK is already low at the beginning of a command.

6.1.2 Dual SPI Modes

The

HM25Q128A supports Dual SPI Operation when using the Fast Read Dual Output (3Bh) and Fast

Dual I/O (BBh) instruction. These features allow data to be transferred from the device at twice the rate

possible with the standard SPI. These instructions are ideal for quickly downloading code to RAM upon

Power-up (code-shadowing) or for executing non-speed-critical code directly from the SPI bus (XIP). When

using Dual SPI commands, the DI and DO pins become bidirectional I/O pins: IO0 and IO1.

6.1.3 Quad SPI Modes

The

HM25Q128A

supports Quad SPI operation when using the Fast Read Quad Output (6Bh), Fast Read

Quad I/O (EBh) instruction, Word Read Quad I/O(E7h), and Octal Word Read Quad I/O(E3h). These

instructions allow data to be transferred to or from the device four times the rate of ordinary Serial Flash. The

Quad Read instructions offer a significant improvement in continuous and random access transfer rates

HM25Q128A

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