T25S16AFEPR datasheet(21/74 Pages) HMSEMI

21 / 74 page

allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI

instructions, the DI and DO pins become bidirectional IO0 and IO1, and the WP# and HOLD# / RESET# pins

become IO2 and IO3 respectively. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in

Status Register-2 to be set.

6.1.4 QPI Function

The

HM25Q128A supports Quad Peripheral Interface (QPI) operations when the device is switched from

Standard/Dual/Quad SPI mode to QPI mode using the “Enter QPI (38h)” instruction. The typical SPI protocol

requires that the byte-long instruction code being shifted into the device only via DI pin in eight serial clocks.

The QPI mode utilizes all four IO pins to input the instruction code, thus only two serial clocks are required.

This can significantly reduce the SPI instruction overhead and improve system performance in an XIP

environment. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only one mode can be active at

any given time. “Enter QPI (38h)” and “Exit QPI (FFh)” instructions are used to switch between these two

modes. Upon power-up or after a software reset using “Reset (99h)” instruction, the default state of the device

is Standard/Dual/Quad SPI mode. To enable QPI mode, the non-volatile Quad Enable bit (QE) in Status

and IO1, and the WP# and HOLD# / RESET# pins become IO2 and IO3 respectively.

6.1.5 Hold Function

For Standard SPI and Dual SPI operations, the HOLD# / RESET# (IO3) signal allows the device interface

operation to be paused while it is actively selected (when CS# is low). The Hold function may be useful in

cases where the SPI data and clock signals are shared with other devices. For example, if the page buffer is

only partially written when a priority interrupt requires use of the SPI bus, the Hold function can save the state

of the interface and the data in the buffer so programming command can resume where it left off once the bus

is available again. The Hold function is only available for standard SPI and Dual SPI operation, not during

Quad SPI.

To initiate a Hold condition, the device must be selected with CS# low. A Hold condition will activate on

the falling edge of the HOLD# signal if the CLK signal is already low. If the CLK is not already low the Hold

condition will activate after the next falling edge of CLK. The Hold condition will terminate on the rising edge of

the HOLD# signal if the CLK signal is already low. If the CLK is not already low the Hold condition will

terminate after the next falling edge of CLK. During a Hold condition, the Serial Data Output, (DO) or IO0 and

IO1, are high impedance and Serial Data Input, (DI) or IO0 and IO1, and Serial Clock (CLK) are ignored. The

Chip Select (CS#) signal should be kept active (low) for the full duration of the Hold operation to avoid

resetting the internal logic state of the device.

6.1.6 Software Reset & Hardware RESET# pin

The

HM25Q128A can be reset to the initial power-on state by a software Reset sequence, either in SPI

mode or QPI mode. This sequence must include two consecutive commands: Enable Reset (66h) & Reset

(99h). If the command sequence is successfully accepted, the device will take approximately 10us (tRST) to

reset. No command will be accepted during the reset period.

HM25Q128A

can also be configured to utilize a hardware RESET# pin. The HRSW bit in the Status

default), the pin acts as a HOLD# pin as described above; when HRSW =1, the pin acts as a RESET# pin.

Drive the RESET# pin low for a minimum period of ~1us (tRESET*) will reset the device to its initial power-on

state. Any on-going Program/Erase operation will be interrupted and data corruption may happen. While

RESET# is low, the device will not accept any command input.

If QE bit is set to 1, the HOLD# or RESET# function will be disabled, the pin will become one of the four

data I/O pins.

Hardware RESET# pin has the highest priority among all the input signals. Drive RESET# low for a

minimum period of ~1us (tRESET*) will interrupt any on-going external/internal operations, regardless the status

of other SPI signals (CS#, CLK, DI, DO, WP# and/or HOLD#).

Note:

HM25Q128A

T25S16AFEPR Datenblatt(PDF) 21 Page - Shenzhen Huazhimei Semiconductor Co., Ltd

T25S16AFEPR Datenblatt(HTML) 21 Page - Shenzhen Huazhimei Semiconductor Co., Ltd

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

Datenblatt Download

Link URL