STM32U595AI datasheet(62/377 Pages) STMICROELECTRONICS

62 / 377 page

Functional overview

STM32U59xxx

62/377

DS13633 Rev 1

The OCTOSPI supports the following protocols with associated frame formats:

•

the standard frame format with the command, address, alternate byte, dummy cycles

and data phase

•

the HyperBus™ frame format

The OCTOSPI offers the following features:

•

Three functional modes: Indirect, Status-polling, and Memory-mapped

•

Read and write support in Memory-mapped mode

•

Supports for single, dual, quad and octal communication

•

Dual-quad mode, where eight bits can be sent/received simultaneously by accessing

two quad memories in parallel.

•

SDR (single-data rate) and DTR (double-transfer rate) support

•

Data strobe support

•

Fully programmable opcode

•

Fully programmable frame format

•

HyperBus support

•

Integrated FIFO for reception and transmission

•

8-, 16-, and 32-bit data accesses allowed

•

DMA channel for Indirect mode operations

•

Interrupt generation on FIFO threshold, timeout, operation complete, and access error

3.27.1

OCTOSPI TrustZone security

When the TrustZone security is enabled, the whole OCTOSPI bank is secure after reset.

Up to two nonsecure area can be configured thought the TZSC MPCWM1 and MPCWM5

controllers with a granularity of 64 Kbytes.

The OCTOSPI registers can be configured as secure through the TZSC controller.

3.28

OCTOSPI I/O manager (OCTOSPIM)

The OCTOSPI I/O manager is a low-level interface enabling:

•

efficient OCTOSPI pin assignment with a full I/O matrix (before alternate function map)

•

multiplex of Single-, Dual-, Quad-, Octal-SPI interfaces over the same bus and hence

support memories embedded in a multichip package

The OCTOSPIM main features are:

•

Supports up to two Single-, Dual-, Quad-, Octal-SPI interfaces

•

Supports up to two ports for pin assignment

•

Fully programmable I/O matrix for pin assignment by function (data/control/clock)

3.29

Delay block (DLYB)

The delay block (DLYB) is used to generate an output clock that is dephased from the input

clock. The phase of the output clock must be programmed by the user application. The

output clock is then used to clock the data received by another peripheral such as

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