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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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STM32U595AI Datenblatt(PDF) 94 Page - STMicroelectronics |
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STM32U595AI Datenblatt(HTML) 94 Page - STMicroelectronics |
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94 / 377 page  Functional overview STM32U59xxx 94/377 DS13633 Rev 1 3.53 USB Type-C /USB Power Delivery controller (UCPD) The device embeds one controller (UCPD) compliant with USB Type-C Cable and Connector Specification release 2.0 and USB Power Delivery Rev. 3.0 specifications. The controller uses specific I/Os supporting the USB Type-C and USB power delivery requirements, featuring: • USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors • “Dead battery” support • USB power delivery message transmission and reception • FRS (fast role swap) support The digital controller handles notably: • USB Type-C level detection with debounce, generating interrupts • FRS detection, generating an interrupt • Byte-level interface for USB power delivery payload, generating interrupts (DMA compatible) • USB power delivery timing dividers (including a clock prescaler) • CRC generation/checking • 4b5b encode/decode • Ordered sets (with a programmable ordered set mask at receive) • Frequency recovery in receiver during preamble The interface offers low-power operation compatible with Stop mode, maintaining the capacity to detect incoming USB power delivery messages and FRS signaling. 3.54 Development support 3.54.1 Serial-wire/JTAG debug port (SWJ-DP) The Arm SWJ-DP interface is embedded and is a combined JTAG and serial-wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using two pins only instead of five required by the JTAG (JTAG pins can be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 3.54.2 Embedded Trace Macrocell The Arm Embedded Trace Macrocell (ETM) provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the devices through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The ETM operates with third party debugger software tools. |
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