STM32U595AI datasheet(66/377 Pages) STMICROELECTRONICS

66 / 377 page

Functional overview

STM32U59xxx

66/377

DS13633 Rev 1

•

Conversion modes

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Single mode: the ADC converts a single channel. The conversion is triggered by

a special event.

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Scan mode: the ADC scans and converts a sequence of channels.

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Continuous mode: the ADC converts continuously selected inputs.

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Discontinuous mode: the ADC converts a subset of the conversion sequence.

•

Interrupt generation when the ADC is ready, at end of sampling, end of conversion

(regular or injected), end of sequence conversion (regular or injected), analog

watchdog 1, 2 or 3 or when an overrun event occurs

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Three analog watchdogs

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Filtering to ignore out-of-range data

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ADC input range: VSSA < VIN < VREF+

Note:

The ADC1/2 analog block clock frequency must be between 5 MHz and 55 MHz.

3.31.2

Analog-to-digital converter 4 (ADC4)

The 12-bit ADC4 is a successive approximation analog-to-digital converter. It has up to

25 multiplexed channels allowing it to measure signals from 19 external and six internal

sources. A/D conversion of the various channels can be performed in Single, Continuous,

Scan or Discontinuous mode. The result of the ADC is stored in a left-aligned or

right-aligned 16-bit data register.

The analog watchdog feature allows the application to detect if the input voltage goes

outside the user-defined higher or lower thresholds.

An efficient low-power mode is implemented to allow very low consumption at low

frequency. The ADC4 is autonomous in low-power modes down to Stop 2 mode.

A built-in hardware oversampler allows analog performances to be improved while

off-loading the related computational burden from the CPU.

The ADC4 main features are:

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High performance

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12-, 10-, 8- or 6-bit configurable resolution

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A/D conversion time: 0.4 µs for 12-bit resolution (2.5 MHz), faster conversion

times obtained by lowering resolution

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Self-calibration

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Programmable sampling time

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Data alignment with built-in data coherency

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DMA support

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Low-power

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HCLK frequency reduced for low-power operation while still keeping optimum

ADC performance

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Wait mode: ADC overrun prevented in applications with low frequency HCLK

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Auto-off mode: ADC automatically powered off except during the active

conversion phase, dramatically reducing the ADC power consumption

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Autonomous mode: In low-power modes down to Stop 2 mode, the ADC4 is

automatically switched on when a trigger occurs to start conversion, and it is

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