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STM32U595AI Datenblatt(PDF) 28 Page - STMicroelectronics

Teilenummer STM32U595AI
Bauteilbeschribung  Ultra-low-power Arm® Cortex®-M33 32-bit MCUTrustZone®FPU,240 DMIPS, up to 4 MB Flash, 2.5 MB SRAM, LTDC, MIPI® DSI
PDF  377 Pages
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Hersteller  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32U595AI Datenblatt(HTML) 28 Page - STMicroelectronics

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Functional overview
STM32U59xxx
28/377
DS13633 Rev 1
3.5
Embedded SRAMs
Six SRAMs are embedded in the STM32U59xxx devices, each with specific features.
SRAM1, SRAM2, SRAM3 and SRAM5 are the main SRAMs. SRAM4 is in the SRAM used
for peripherals LPBAM (low-power background autonomous mode) in Stop 2 mode.
These SRAMs are made of several blocks that can be powered down in Stop mode to
reduce consumption:
•
SRAM1: 12 64-Kbyte blocks (total 768 Kbytes)
•
SRAM2: 8-Kbyte + 56-Kbyte blocks (total 64 Kbytes) with optional ECC. In addition
SRAM2 blocks can be retained in Standby mode.
•
SRAM3: 13 64-Kbyte blocks (total 832 Kbytes) with optional ECC. When ECC is
enabled, 256 Kbytes support ECC and 512 Kbytes of SRAM3 can be accessed
without ECC.
•
SRAM4: 16 Kbytes
•
SRAM5: 13 64-Kbyte blocks (total 832 Kbytes)
•
BKPSRAM (backup SRAM): 2 Kbytes with optional ECC. The BKPSRAM can be
retained in all low-power modes and when VDD is off in VBAT mode, but not in
Shutdown mode.
3.5.1
SRAMs TrustZone security
When the TrustZone security is enabled, all SRAMs are secure after reset. The SRAM1,
SRAM2, SRAM3, SRAM4 and SRAM5 can be programmed as secure or nonsecure by
blocks, using the MPCBB (block-based memory protection controller).
The granularity of SRAM secure block based is a page of 512 bytes. Backup SRAM regions
can be programmed as secure or nonsecure with watermark, using the TZSC (TrustZone
security controller) in the GTZC (global TrustZone controller).
3.5.2
SRAMs privilege protection
The SRAM1, SRAM2, SRAM3, SRAM4 and SRAM5 can be programmed as privileged or
unprivileged by blocks, using the MPCBB. The granularity of SRAM privilege block based is
a page of 512 bytes. Backup SRAM regions can be programmed as privileged or
unprivileged with watermark, using the TZSC (TrustZone security controller) in the GTZC
(global TrustZone controller).
3.6
TrustZone security architecture
The security architecture is based on Arm TrustZone with the Armv8-M main extension.
The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register.
When the TrustZone is enabled, the SAU (security attribution unit) and IDAU
(implementation defined attribution unit) define the access permissions based on secure
and nonsecure state.
•
SAU: up to eight SAU configurable regions are available for security attribution.
•
IDAU: It provides a first memory partition as nonsecure or nonsecure callable
attributes. It is then combined with the results from the SAU security attribution and
the higher security state is selected.



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