PIC16F570 datasheet(23/134 Pages) MICROCHIP

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 2012-2014 Microchip Technology Inc.

DS40001652C-page 23

PIC16F527

5.0

SELF-WRITABLE FLASH DATA

MEMORY CONTROL

Flash Data memory consists of 64 bytes of self-

writable memory and supports a self-write capability

that can write four bytes of memory at one time. Data

to be written to the self-writable data memory is first

written into four write latches before writing the data to

Flash memory.

Although each Flash data memory location is 12 bits

wide, access is limited to the lower eight bits. The

upper four bits will automatically default to ‘1’ in any

self-write procedure. The lower eight bits are fully

readable and writable during normal operation and

throughout the full VDD range.

The self-writable Flash data memory is not directly

mapped in the register file space. Instead, it is

indirectly addressed through the Special Function

Registers, EECON, EEDATA and EEADR.

5.1

Reading Flash Data Memory

To read a Flash data memory location the user must:

• Write the EEADR register

• Set the RD bit of the EECON register

The value written to the EEADR register determines

which Flash data memory location is read. Setting the

RD bit of the EECON register initiates the read. Data

from the Flash data memory read is available in the

EEDATA register immediately. The EEDATA register

will hold this value until another read is initiated or it is

modified by a write operation. Program execution is

suspended while the read cycle is in progress.

Execution will continue with the instruction following the

one that sets the WR bit. See Example 5-1 for sample

code.

EXAMPLE 5-1:

READING FROM FLASH

DATA MEMORY

5.1.1

ERASING FLASH DATA MEMORY

A row must be manually erased before writing new

data. The following sequence must be performed for a

single row erase.

Load EEADR with an address in the row to be

erased.

Set the FREE bit to enable the erase.

Set the WREN bit to enable write access to the

array.

Disable interrupts.

Set the WR bit to initiate the erase cycle.

If the WREN bit is not set in the instruction cycle after

the FREE bit is set, the FREE bit will be cleared in

hardware.

If the WR bit is not set in the instruction cycle after the

WREN bit is set, the WREN bit will be cleared in

hardware.

Sample code that follows this procedure is included in

Example 5-2.

Program execution is suspended while the erase cycle

is in progress. Execution will continue with the

instruction following the one that sets the WR bit.

EXAMPLE 5-2:

ERASING A FLASH DATA

MEMORY ROW

Note: Only a BSF command will work to enable

the Flash data memory read documented in

Example 5-1.

other

sequence

commands will work, no exceptions.

MOVLB

0x01

; Switch to Bank 1

MOVF

DATA_EE_ADDR,W;

MOVWF

EEADR

; Data Memory

; Address to read

BSF

EECON, RD

; EE Read

MOVF

EEDATA, W

; W = EEDATA

Note 1: To prevent accidental corruption of the

Flash data memory, an unlock sequence

is required to initiate a write or erase

cycle. This sequence requires that the bit

set instructions used to configure the

EECON register happen exactly as

shown in Example 5-2 and Example 5-3,

depending on the operation requested.

2: In order to prevent any disruptions of self-

writes or row erases performed on the

self-writable

Flash

data

memory,

interrupts should be disabled prior to

executing those routines.

MOVLB

0x01

; Switch to Bank 1

MOVLW

EE_ADR_ERASE

; LOAD ADDRESS OF ROW TO

; ERASE

MOVWF

EEADR

;

BSF

EECON,FREE

; SELECT ERASE

BSF

EECON,WREN

; ENABLE WRITES

BSF

EECON,WR

; INITITATE ERASE

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