PIC16F570 datasheet(50/134 Pages) MICROCHIP

50 / 134 page

PIC16F527

DS40001652C-page 50

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8.11

Interrupts

The interrupt feature allows certain events to preempt

normal program flow. Firmware is used to determine

the source of the interrupt and act accordingly. Some

interrupts can be configured to wake the MCU from

Sleep mode.

These following interrupt sources are available on the

PIC16F527 device:

• Timer0 Overflow

• ADC Completion

• Comparator Output Change

• Interrupt-on-change pin

Refer to the corresponding chapters for details.

8.11.1

OPERATION

Interrupts are disabled upon any device Reset. They

are enabled by setting the following bits:

• GIE bit of the INTCON register

• Interrupt Enable bit(s) for the specific interrupt

event(s)

The enable bits for specific interrupts can be found in

the INTCON1 register. An interrupt is recorded for a

specific interrupt via flag bits found in the INTCON0

The ADC Conversion flag and the Timer0 Overflow

flags will be set regardless of the status of the GIE and

individual interrupt enable bits.

The Comparator and Interrupt-on-change flags must

be enabled for use. One or both of the comparator

outputs can be enabled to affect the interrupt flag by

setting the C1WU bit in the CM1CON0 register and the

C2WU bit in the CM2CON0 register. The Interrupt-on-

change flag is enabled by setting the RAWU bit in the

OPTION register.

The following events happen when an interrupt event

occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

• Current Program Counter (PC) is pushed onto the

stack

• Several registers are automatically switched to a

secondary set of registers to store critical data.

(See Section 8.12 “Automatic Context Switch-

ing”)

• PC is loaded with the interrupt vector 0004h

The firmware within the Interrupt Service Routine (ISR)

should determine the source of the interrupt by polling

the interrupt flag bits. The interrupt flag bits must be

cleared before exiting the ISR to avoid repeated

interrupts. Because the GIE bit is cleared, any interrupt

that occurs while executing the ISR will be recorded

through its interrupt flag, but will not cause the

processor to redirect to the interrupt vector.

8.12

Automatic Context Switching

While the device is executing from the ISR, a

secondary set of W, STATUS, FSR and BSR registers

are used by the CPU. These registers are still

addressed at the same location, but hold persistent,

independent values for use inside the ISR. This allows

the contents of the primary set of registers to be

unaffected by interrupts in the main line execution. The

contents of the secondary set of context registers are

visible in the SFR map as the IW, ISTATUS, IFSR and

IBSR registers. When executing code from within the

ISR, these registers will read back the main line

context, and vice versa.

The RETFIE instruction exits the ISR by popping the

previous address from the stack, switching back to the

original set of critical registers and setting the GIE bit.

For additional information on a specific interrupt’s

operation, refer to its peripheral chapter.

8.13

Interrupts during Sleep

Any of the interrupt sources can be used to wake from

Sleep. To wake from Sleep, the peripheral must be

operating without the system clock. The interrupt

source must have the appropriate Interrupt Enable

bit(s) set prior to entering Sleep.

On waking from Sleep, if the GIE bit is also set, the

processor will branch to the interrupt vector. Otherwise,

the processor will continue executing instructions after

the SLEEP instruction. The instruction directly after the

SLEEP instruction will always be executed before

branching to the ISR. Refer to the Section 8.10

“Power-down Mode (Sleep)” for more details.

TABLE 8-7:

INTERRUPT PRIORITIES

Note 1: Individual interrupt flag bits may be set,

regardless of the state of any other

enable bits.

2: All interrupts will be ignored while the GIE

bit is cleared. Any interrupt occurring

while the GIE bit is clear will be serviced

when the GIE bit is set again.

3: All interrupts should be disabled prior to

executing writes or row erases in the self-

writable Flash data memory.

Vector or

In Sleep

GIE

WUR

Wake-up and Vector

Wake-up Reset

Wake-up Inline

Watchdog

Wake-up Inline

Watchdog

Wake-up Reset

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