| Datenblatt-Suchmaschine für elektronische Bauteile |
|
PIC16F570 Datenblatt(PDF) 57 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
PIC16F570 Datenblatt(HTML) 57 Page - Microchip Technology |
|
57 / 134 page ![]() 2012-2014 Microchip Technology Inc. DS40001652C-page 57 PIC16F527 9.1.6 ANALOG CONVERSION RESULT REGISTER The ADRES register contains the results of the last conversion. These results are present during the sampling period of the next analog conversion process. After the sampling period is over, ADRES is cleared (= 0). A ‘leading one’ is then right shifted into the ADRES to serve as an internal conversion complete bit. As each bit weight, starting with the MSB, is converted, the leading one is shifted right and the converted bit is stuffed into ADRES. After a total of nine right shifts of the ‘leading one’ have taken place, the conversion is complete; the ‘leading one’ has been shifted out and the GO/DONE bit is cleared. If the GO/DONE bit is cleared in software during a conversion, the conversion stops and the ADIF bit will not be set to a ‘1’. The data in ADRES is the partial conversion result. This data is valid for the bit weights that have been converted. The position of the ‘leading one’ determines the number of bits that have been converted. The bits that were not converted before the GO/DONE was cleared are unrecoverable. REGISTER 9-1: ADCON0: A/D CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 ADCS<1:0>: ADC Conversion Clock Select bits 00 =FOSC/16 01 =FOSC/8 10 =FOSC/4 11 = INTOSC/4 bit 5-2 CHS<3:0>: ADC Channel Select bits(1) 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5) 0110 = Channel 6 (AN6) 0111 = Channel 7 (AN7) 1xxx = Reserved 1111 = 0.6V Fixed Input Reference (VFIR) bit 1 GO/DONE: ADC Conversion Status bit(2) 1 = ADC conversion in progress. Setting this bit starts an ADC conversion cycle. This bit is automatically cleared by hardware when the ADC is done converting. 0 = ADC conversion completed/not in progress. Manually clearing this bit while a conversion is in process terminates the current conversion. bit 0 ADON: ADC Enable bit 1 = ADC module is operating 0 = ADC module is shut-off and consumes no power Note 1: CHS<3:0> bits default to 1 after any Reset. 2: If the ADON bit is clear, the GO/DONE bit cannot be set. |
|
Link URL |
| War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Link zum Datenblatt | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |