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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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PIC16F570 Datenblatt(PDF) 15 Page - Microchip Technology |
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PIC16F570 Datenblatt(HTML) 15 Page - Microchip Technology |
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15 / 134 page  2012-2014 Microchip Technology Inc. DS40001652C-page 15 PIC16F527 Bank 2 N/A W(2) Working Register (W) xxxx xxxx xxxx xxxx N/A TRIS I/O Control Registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler 1111 1111 1111 1111 N/A BSR(2) — — — — — — BSR1 BSR0 ---- -000 ---- -0uu 40h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu 41h TMR0 Timer0 module Register xxxx xxxx uuuu uuuu 42h PCL(1) Low-order eight bits of PC 1111 1111 1111 1111 43h STATUS(2) Reserved Reserved PA0 TO PD ZDC C -001 1xxx -00q qqqq 44h FSR(2) — Indirect data memory address pointer 0xxx xxxx 0uuu uuuu 45h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — 1111 111- uuuu uuu- 46h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu 47h PORTB RB7 RB6 RB5 RB4 — — — — xxxx ---- uuuu ---- 48h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 49h ADCON0 ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 1111 1100 1111 1100 4Ah ADRES ADC Conversion Result xxxx xxxx uuuu uuuu 4Bh INTCON0 ADIF CWIF T0IF RAIF — — — GIE 0000 ---0 0000 ---0 Bank 3 N/A W(2) Working Register (W) xxxx xxxx xxxx xxxx N/A TRIS I/O Control Registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler 1111 1111 1111 1111 N/A BSR(2) — — — — — — BSR1 BSR0 ---- -000 ---- -0uu 60h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu 61h IW(3) Interrupt Working Register. (Addressed also as W register when within ISR) xxxx xxxx xxxx xxxx 62h PCL(1) Low-order eight bits of PC 1111 1111 1111 1111 63h STATUS(2) Reserved Reserved PA0 TO PD ZDC C -001 1xxx -00q qqqq 64h FSR(2) — Indirect data memory address pointer 0xxx xxxx 0uuu uuuu 65h INTCON1 ADIE CWIE T0IE RAIE — — — WUR 0000 ---0 0000 ---0 66h ISTATUS(3) Reserved Reserved PA0 TO PD ZDC C -xxx xxxx -00q qqqq 67h IFSR(3) — Indirect data memory address pointer 0xxx xxxx 0uuu uuuu 68h IBSR(3) — — — — — — BSR1 BSR0 ---- -0xx ---- -0uu 69h OPACON — — — — — — OPA2ON OPA1ON ---- --00 ---- --00 6Bh INTCON0 ADIF CWIF T0IF RAIF — — — GIE 0000 ---0 0000 ---0 TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR Value on all other Resets Legend: x = unknown, u = unchanged, – = unimplemented, read as '0' (if applicable), q = value depends on condition. Shaded cells = unimplemented or unused Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.6 “Program Counter” for an explanation of how to access these bits. 2: Registers are implemented as two physical registers. When executing from within an ISR, a secondary register is used at the same logical location. Both registers are persistent. See Section 8.11 “Interrupts”. 3: These registers show the contents of the registers in the other context: ISR or main line code. See Section 8.11 “Interrupts”. |
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