PIC16F570 datasheet(47/134 Pages) MICROCHIP

47 / 134 page

 2012-2014 Microchip Technology Inc.

DS40001652C-page 47

PIC16F527

FIGURE 8-11:

WATCHDOG TIMER BLOCK DIAGRAM

TABLE 8-5:

REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

8.8

Time-out Sequence (TO) and

Power-down (PD) Reset Status

The TO and PD bits in the STATUS register can be

tested to determine if a Reset condition has been

caused by a power-up condition, a MCLR or Watchdog

Timer (WDT) Reset.

TABLE 8-6:

TO/PD STATUS AFTER RESET

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

page

OPTION

RAWU

RAPU

T0SC

T0SE

PSA

PS2

PS1

PS0

Legend: Shaded boxes = Not used by Watchdog Timer.

(Figure 7-1)

Postscaler

Note 1: PSA, PS<2:0> are bits in the OPTION register.

WDT Time-out

Watchdog

Time

From Timer0 Clock Source

WDT Enable

Configuration

Bit

PSA

Postscaler

8-to-1 MUX

PS<2:0>(1)

(Figure 7-4)

To Timer0

PSA(1)

MUX

Reset Caused By

WDT wake-up from Sleep

WDT time-out (not from Sleep)

MCLR wake-up from Sleep

Power-up or Brown-out Reset

MCLR not during Sleep

Legend: u = unchanged

Note 1:

The TO and PD bits maintain their status

(u) until a Reset occurs. A low pulse on

the MCLR input does not change the TO

and PD Status bits.

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