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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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PIC16F570 Datenblatt(PDF) 14 Page - Microchip Technology |
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PIC16F570 Datenblatt(HTML) 14 Page - Microchip Technology |
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14 / 134 page  PIC16F527 DS40001652C-page 14 2012-2014 Microchip Technology Inc. TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR Value on all other Resets Bank 0 N/A W(2) Working Register (W) xxxx xxxx xxxx xxxx N/A TRIS I/O Control Registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler 1111 1111 1111 1111 N/A BSR(2) — — — — — — BSR1 BSR0 ---- -000 ---- -0uu 00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu 01h TMR0 Timer0 module Register xxxx xxxx uuuu uuuu 02h PCL(1) Low-order eight bits of PC 1111 1111 1111 1111 03h STATUS(2) Reserved Reserved PA0 TO PD ZDC C -001 1xxx -00q qqqq 04h FSR(2) — Indirect data memory address pointer 0xxx xxxx 0uuu uuuu 05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — 1111 111- uuuu uuu- 06h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu 07h PORTB RB7 RB6 RB5 RB4 — — — — xxxx ---- uuuu ---- 08h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 09h ADCON0 ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 1111 1100 1111 1100 0Ah ADRES ADC Conversion Result xxxx xxxx uuuu uuuu 0Bh INTCON0 ADIF CWIF T0IF RAIF — — — GIE 0000 ---0 0000 ---0 Bank 1 N/A W(2) Working Register (W) xxxx xxxx xxxx xxxx N/A TRIS I/O Control Registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler 1111 1111 1111 1111 N/A BSR(2) — — — — — — BSR1 BSR0 ---- -000 ---- -0uu 20h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu 21h EECON — — — FREE WRERR WREN WR RD ---0 0000 ---0 0000 22h PCL(1) Low-order eight bits of PC 1111 1111 1111 1111 23h STATUS(2) Reserved Reserved PA0 TO PD ZDC C -001 1xxx -00q qqqq 24h FSR(2) — Indirect data memory address pointer 0xxx xxxx 0uuu uuuu 25h EEDATA Self Read/Write Data xxxx xxxx uuuu uuuu 26h EEADR — — Self Read/Write Address --xx xxxx --uu uuuu 27h CM1CON0 C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU 1111 1111 quuu uuuu 28h CM2CON0 C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU 1111 1111 quuu uuuu 29h VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 001- 0000 uuu- uuuu 2Ah ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 2Bh INTCON0 ADIF CWIF T0IF RAIF — — — GIE 0000 ---0 0000 ---0 Legend: x = unknown, u = unchanged, – = unimplemented, read as '0' (if applicable), q = value depends on condition. Shaded cells = unimplemented or unused Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.6 “Program Counter” for an explanation of how to access these bits. 2: Registers are implemented as two physical registers. When executing from within an ISR, a secondary register is used at the same logical location. Both registers are persistent. See Section 8.11 “Interrupts”. 3: These registers show the contents of the registers in the other context: ISR or main line code. See Section 8.11 “Interrupts”. |
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