| Datenblatt-Suchmaschine für elektronische Bauteile |
|
L9805 Datenblatt(PDF) 65 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
L9805 Datenblatt(HTML) 65 Page - STMicroelectronics |
|
65 / 103 page ![]() 65/103 L9805 CONTROLLER AREA NETWORK (Cont’d) 5.6.3.4 Bit Timing Logic The bit timing logic monitors the serial bus-line and performs sampling and adjustment of the sample point by synchronizing on the start-bit edge and re- synchronization on following edges. Its operation may be explained simply when the nominal bit time is divided into three segments as follows: – Synchronisation segment (SYNC_SEG): a bit change is expected to lie within this time seg- ment. It has a fixed length of one time quanta (1 x tCAN). – Bit segment 1 (BS1): defines the location of the sample point. It includes the PROP_SEG and PHASE_SEG1 of the CAN standard. Its duration is programmable between 1 and 16 time quanta but may be automatically lengthened to compen- sate for positive phase drifts due to differences in the frequency of the various nodes of the net- work. – Bit segment 2 (BS2): defines the location of the transmit point. It represents the PHASE_SEG2 of the CAN standard. Its duration is programma- ble between 1 and 8 time quanta but may also be automatically shortened to compensate for neg- ative phase drifts. The resynchronization jump width (RJW) defines an upper bound to the amount of lengthening or shortening of the bit segments. It is programmable between 1 and 4 time quanta. A valid edge is defined as the first transition in a bit time from dominant to recessive bus level provid- ed the controller itself does not send a recessive bit. If a valid edge is detected in BS1 instead of SYNC_SEG, BS1 is extended by up to RJW so that the sample point is delayed. Conversely, if a valid edge is detected in BS2 in- stead of SYNC_SEG, BS2 is shortened by up to RJW so that the transmit point is moved earlier. As a safeguard against programming errors, the configuration of the Bit Timing Register (BTR) is only possible while the device is in STANDBY mode. Figure 1. Bit Timing SYNC_SEG BIT SEGMENT 1 (BS1) BIT SEGMENT 2 (BS2) NOMINAL BIT TIME 1 x tCAN tBS1 tBS2 SAMPLE POINT TRANSMIT POINT |
|
Link URL |
| War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Link zum Datenblatt | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |