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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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L9805 Datenblatt(PDF) 85 Page - STMicroelectronics |
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L9805 Datenblatt(HTML) 85 Page - STMicroelectronics |
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85 / 103 page  85/103 L9805 same higher part of the address, all the 4 groups of data latches will be written, and they will be ready to write a whole row of the EEPROM matrix, as soon as E2PGM goes high and the charge-pump starts. If only one write instruction is executed be- fore E2PGM goes high, only one group of data latches will be selected and only one byte of the matrix will be written. At the end of the program- ming cycle, E2LAT bit is automatically cleared, and the data latches are cleared. Bit 0 = E2PGM: Programming Control. This bit is set by software to begin the program- ming cycle. At the end of the programming cycle, this bit is cleared by hardware and an interrupt is generated if the E2ITE bit is set. 0: Programming finished or not started 1: Programming cycle is in progress Note: if the E2PGM bit is cleared during the pro- gramming cycle, the memory data is not guaran- teed. Note: Care should be taken during the program- ming cycle. Writing to the same memory location will over-program the memory (logical AND be- tween the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of E2LAT bit. It is not possible to read the latched data. Special management of wrong EEPROM access: If a read happens while E2LAT=1, then the data bus will not be driven. If a write access happens while E2LAT=0, then the data on the bus will not be latched. The data latches are cleared when the user sets E2LAT bit. |
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