L9805 datasheet(69/103 Pages) STMICROELECTRONICS

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L9805

CONTROLLER AREA NETWORK (Cont’d)

BAUD RATE PRESCALER REGISTER (BRPR)

Address: 005Dh - Read/Write in Stand-by mode

Reset Value: 00h

RJW[1:0] determine the maximum number of time

quanta by which a bit period may be shortened or

lengthened to achieve resynchronization.

tRJW = tCAN * (RJW + 1)

BRP[5:0] determine the CAN system clock cycle

time or time quanta which is used to build up the in-

dividual bit timing.

tCAN = tCPU * (BRP + 1)

Where tCPU = time period of the CPU clock.

The resulting baud rate can be computed by the for-

mula:

Note: Writing to this register is allowed only in

Stand-by mode to prevent any accidental CAN

protocol violation through programming errors.

BIT TIMING REGISTER (BTR)

Address: 005Eh - Read/Write in Stand-by mode

Reset Value: 23h

BS2[2:0] determine the length of Bit Segment 2.

tBS2 = tCAN * (BS2 + 1)

BS1[3:0] determine the length of Bit Segment 1.

tBS1 = tCAN * (BS1 + 1)

Note: Writing to this register is allowed only in

Stand-by mode to prevent any accidental CAN

protocol violation through programming errors.

PAGE SELECTION REGISTER (PSR)

Address: 005Fh - Read/Write

Reset Value: 00h

PAGE[2:0] determine which buffer or filter page is

mapped at addresses 0060h to 006Fh.

RJW1

RJW0

BRP5

BRP4

BRP3

BRP2

BRP1

BRP0

CPU

BR P

()

BS1

BS 23

()

----------------------------------------------------------------------------------------------

BS22

BS21

BS20

BS13

BS12

BS11

BS10

PAGE2 PAGE1

PAGE0

PAGE2

PAGE1

PAGE0

Page Title

000

Diagnosis

001

Buffer 1

010

Buffer 2

011

Buffer 3

100

Filters

101

Reserved

110

Reserved

111

Reserved

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