L9805 datasheet(68/103 Pages) STMICROELECTRONICS

68 / 103 page

68/103

L9805

CONTROLLER AREA NETWORK (Cont’d)

CONTROL/STATUS REGISTER (CSR)

Address: 005Ch - Read/Write

Reset Value: 00h

Bit 6 = BOFF Bus-Off State

− Read Only

Set by hardware to indicate that the node is in bus-

off state, i.e. the Transmit Error Counter exceeds

255.

Reset by hardware to indicate that the node is in-

volved in bus activities.

Bit 5 = EPSV Error Passive State

− Read Only

Set by hardware to indicate that the node is error

passive.

Reset by hardware to indicate that the node is either

error active (BOFF = 0) or bus-off.

Bit 4 = SRTE Simultaneous Receive/Transmit En-

able

− Read/Set/Clear

Set by software to enable simultaneous transmis-

sion and reception of a message passing the ac-

ceptance filtering. Allows to check the integrity of

the communication path.

Reset by software to discard all messages trans-

mitted by the node. Allows remote and data frames

to share the same identifier.

Bit 3 = NRTX No Retransmission

− Read/Set/Clear

Set by software to disable the retransmission of un-

successful messages.

Cleared by software to enable retransmission of

messages until success is met.

Bit 2 = FSYN Fast Synchronization

− Read/Set/Clear

Set by software to enable a fast resynchronization

when leaving standby mode, i.e. wait for only 11 re-

cessive bits in a row.

Cleared by software to enable the standard resyn-

chronization when leaving standby mode, i.e. wait

for 128 sequences of 11 recessive bits.

Bit 1 = WKPS Wake-up Pulse

− Read/Set/Clear

Set by software to generate a dominant pulse when

leaving standby mode.

Cleared by software for no dominant wake-up

pulse.

Bit 0 = RUN CAN Enable

− Read/Set/Clear

Set by software to leave stand-by mode after 128

sequences of 11 recessive bits or just 11 recessive

bits if FSYN is set.

Cleared by software to request a switch to the

stand-by or low-power mode as soon as any on-go-

ing transfer is complete. Read-back as 1 in the

meantime to enable proper signalling of the stand-

by state. The CPU clock may therefore be safely

switched OFF whenever RUN is read as 0.

BOFF

EPSV

SRTE

NRTX

FSYN WKPS

RUN

L9805 Datenblatt(PDF) 68 Page - STMicroelectronics

L9805 Datenblatt(HTML) 68 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL