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RZ/T2L Datenblatt(PDF) 51 Page - Renesas Technology Corp |
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RZ/T2L Datenblatt(HTML) 51 Page - Renesas Technology Corp |
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51 / 103 page ![]() CKIO tDACD tDACD Tr Tc4 A25 to A0 tAD1 tAD1 tCSD1 tRWD1 A12/A11*1 RD/WR# tCSD1 DACK*2 Tc1 Tc2 Tde tRWD1 D15 to D0 tBSD BS# tBSD Row address Column address tAD1 tAD1 tAD1 tAD1 READ command CS3#, CS2# RAS# tRASD1 tRASD1 tCASD1 CAS# tCASD1 DQMLU, DQMLL tDQMD1 tDQMD1 tRDH2 tRDS2 (High) CKE Tc3 Td4 Td1 Td2 Td3 (1 to 4) tAD1 tAD1 tAD1 tAD1 READA command tRDH2 tRDS2 Trw Note 1. Address pin to be connected to A10 of SDRAM. Note 2. DACK is waveform when active-low is specified. Figure 2.22 Synchronous DRAM burst-read bus cycle (read for 4 cycles) (with auto precharge, CAS latency 2, WTRCD = 1 cycle, WTRP = 0 cycles) RZ/T2L Datasheet 2. Electrical Characteristics R01DS0409EJ0130 Rev.1.30 Feb 27, 2026 Page 51 of 103 |
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