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RZ/T2L Datenblatt(PDF) 80 Page - Renesas Technology Corp |
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RZ/T2L Datenblatt(HTML) 80 Page - Renesas Technology Corp |
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80 / 103 page ![]() SSLn0 to SSLn3 output tLEAD SPI tSSLr, tSSLf RSPCKn CPOL = 1 output (n = 0 to 3) tLAG tTD RSPCKn CPOL = 0 output tSU tH MSB IN DATA LSB IN MSB IN MISOn input MOSIn output MSB OUT tDr, tDf tOD DATA tOH LSB OUT MSB OUT IDLE Figure 2.67 SPI timing (Master, Motorola SPI, CPHA = 1) SSLn0 input tLEAD SPI RSPCKn CPOL = 1 input (n = 0 to 3) tLAG tTD RSPCKn CPOL = 0 input tSU tH MSB IN DATA LSB IN MSB IN MISOn output MOSIn input MSB OUT tDr, tDf tOH DATA tOD LSB OUT MSB OUT Invalid DATA tSA tREL Figure 2.68 SPI timing (Slave, Motorola SPI, CPHA = 0) RZ/T2L Datasheet 2. Electrical Characteristics R01DS0409EJ0130 Rev.1.30 Feb 27, 2026 Page 80 of 103 |
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