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RZ/T2L Datenblatt(PDF) 7 Page - Renesas Technology Corp

Teilenummer RZ/T2L
Bauteilbeschribung  RZ Arm-based High-end 32 & 64-bit MPUs
PDF  103 Pages
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

RZ/T2L Datenblatt(HTML) 7 Page - Renesas Technology Corp

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Table 1.8
Communication interfaces (2 of 2)
Feature
Functional description
Serial peripheral interface (SPI)
● 4 channels
● SPI transfer facility
Using the MOSI (master out slave in), MISO (master in slave out), SSL (slave select), and
RSPCK (SPI clock) signals enables serial transfer through SPI operation (four lines) or
clock-synchronous operation (three lines) capable of handling serial transfer as a master or
slave
● Data formats
– Switching between MSB first and LSB first
– Transfer bit length selectable to 4 - 32 bits
– 32 bits × 4-stage FIFO transmit and receive buffers
– Up to four frames can be transmitted or received in a single transfer operation (with
each frame having up to 32 bits)
● RSPCK can be stopped automatically with the reception buffer full for master reception
Expanded serial peripheral interface
(xSPI)
● 2 channels
● Comply with JESD251
● Multiple slave up to 2 slaves
● Protocol mode: 1/4/8pin with SDR/DDR
1S-1S-1S, 4S-4D-4D, 8D-8D-8D
● Support OctaFlash, OctaRAM, HyperFlash and HyperRAM
● Protocol mode: 2/4pin with SDR compatible with QSPI
1S-2S-2S, 2S-2S-2S
1S-4S-4S, 4S-4S-4S
● Configurable address length
● Configurable initial access latency cycle
● Support XiP mode
● Support up to 256 MB address space
● Prefetch function for burst-read with low latency
● Outstanding buffer for burst-write with high throughput
● Manual command configurable up to 4 commands
● Output clock/input strobe port timing shift
● Automatic command after released reset: up to 4 commands
● 1.8 V/3.3 V selectable for xSPI0 and 3.3 V fix for xSPI1
Note 1. EtherCAT is a registered trademark of Beckhoff Automation GmbH, Germany.
Note 2. The product has a device which do not support GMAC and ESC.
Note 3. The product have a device with Classical CAN mode only.
Table 1.9
Analog
Feature
Functional description
12-bit A/D converter (ADC12)
● 12 bits × 2 units (unit 0: 4 channels, unit 1: 4 channels)
● 12-bit resolution
● Conversion time
0.84 µs per channel
● Operating mode
Scan mode (single scan mode, continuous scan mode, or 3 group scan mode)
Group priority control
● Sample-and-hold function
Common sample-and-hold circuit included
In addition, channel-dedicated sample-and-hold function (3 channels: in both unit 0 and unit
1) included
● Sampling variable
Sampling time can be set up for each channel
● Double trigger mode (A/D conversion data duplicated)
● Three ways to start A/D conversion
Software trigger, timer (MTU3, ELC) trigger, external trigger
● Event linking by the ELC
Temperature sensor unit (TSU)
● 1 channel
● Relative precision: ±1°C (typ)
RZ/T2L Datasheet
1. Overview
R01DS0409EJ0130 Rev.1.30
Feb 27, 2026
Page 7 of 103



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