RZSLASHT2L datasheet(86/103 Pages) RENESAS

Teilenummer	RZ/T2L

Bauteilbeschribung	RZ Arm-based High-end 32 & 64-bit MPUs

PDF	103 Pages

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Hersteller	RENESAS [Renesas Technology Corp]

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Table 2.37

ΔΣ interface timing

Parameter

Symbol

Min.

Max.

Unit

Reference figure

DSMIF

Clock cycle

Master

tDScyc

200

Figure 2.78

Slave

200

Clock high level

Master

tDSCKWH

—

Slave

—

Clock low level

Master

tDSCKWL

—

Slave

—

Setup time

Master

tSU

—

Figure 2.79, Figure 2.80

Slave

—

Hold time

Master

—

Slave

—

MCLKn

(n = 0 to 5)

tDScyc

tDSCKWH

tDSCKWL

Figure 2.78

Clock input/output timing

MCLKn

(input or output)

tSU

n = 0 to 5

MDATn

(input)

Figure 2.79

Reception timing (MCLKn rising synchronous)

MCLKn

(input or output)

tSU

MDATn

(input)

Figure 2.80

Reception timing (MCLKn falling synchronous)

2.5.5.14

Ethernet Interface Timing

Conditions:

VOH = VCC18 × 0.5, VOL = VCC18 × 0.5, C = 15 pF (RGMII)*1

RZ/T2L Datasheet

2. Electrical Characteristics

R01DS0409EJ0130 Rev.1.30

Feb 27, 2026

Page 86 of 103

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