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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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WM8953ECS/RV Datenblatt(PDF) 46 Page - Wolfson Microelectronics plc |
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WM8953ECS/RV Datenblatt(HTML) 46 Page - Wolfson Microelectronics plc |
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46 / 100 page  WM8953 Production Data w PD, January 2009, Rev 4.0 46 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 10 MICSHRT_IRQ_ENA 0b MICBIAS short circuit detect IRQ Enable 0 = disabled 1 = enabled R22 (16h) 9 MICDET_IRQ_ENA 0b MICBIAS current detect IRQ Enable 0 = disabled 1 = enabled Table 24 MICBIAS Current Detect Control The current detect function operates according to the following the truth table: LABEL VALUE DESCRIPTION Mic Short Circuit Detect 0 MCDSCTH current threshold not exceeded Mic Short Circuit Detect 1 MCDSCTH current threshold exceeded Mic Current Detect 0 MCDTHR current threshold not exceeded Mic Current Detect 1 MCDTHR current threshold exceeded Table 25 Truth Table for GPIO Output of MICBIAS Current Detect Function CLOCK OUTPUT A clock output (OPCLK) derived from SYSCLK may be output via GPIO3, GPIO4 or GPIO5. SYSCLK is derived from MCLK (either directly, or in conjunction with the PLL), and is used to provide all internal clocking for the WM8953 (see "Clocking and Sample Rates" section for more information). A programmable clock divider OPCLKDIV controls the frequency of the OPCLK output. This clock is enabled by register bit OPCLK_ENA. See “Clocking and Sample Rates” for a definition of this register field. To enable clock output via one or more GPIO pins, the following register settings are required: • AIF_TRIS = 0 • GPIOn_SEL = 0001 for the selected GPIO clock output pin • GPIOn_PU = 0 for the selected GPIO clock output pin • GPIOn_PD = 0 for the selected GPIO clock output pin |
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