WM8953ECSSLASHRV datasheet(74/100 Pages) WOLFSON

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WM8953

Production Data

PD, January 2009, Rev 4.0

EXAMPLE PLL CALCULATION

To generate 12.288MHz SYSCLK from a 12MHz reference clock:

There is a fixed divide by 4 at the PLL output (see Figure 50) followed by a selectable divide by 2 in

the same path. PLL output f2 should be set in the range 90MHz - 100MHz. Enabling the divide by 2

(MCLK_DIV = 10b) sets the required f2 = 4 x 2 x 12.288MHz = 98.304MHz.

There is a selectable pre-scale (divide MCLK by 2) at the PLL input (f1 - see Figure 75). The PLL

frequency ratio f2/f1 must be set in the range 5 - 13. Disabling the MCLK pre-scale (PRESCALE = 0b)

sets the required ratio f2/f1 = 8.192.

The required settings for this example are:

•

MCLK_DIV = 10b

•

PRESCALE = 0b

•

PLL_ENA = 1

•

SDM = 1

•

PLLN = 8 = 8h

•

PLLK = 0.192 = 3126h

EXAMPLE PLL SETTINGS

Table 46 provides example PLL settings for generating common SYSCLK frequencies from a variety

of MCLK reference frequencies.

MCLK

(MHz)

SYSCLK

(MHz)

MCLKDIV

= SYSCLK * 4

* MCLKDIV

PRESCALE

= MCLK/

PRESCALE

= F2/F1

11.2896

90.3168

7.5264

86C2H

12.288

98.304

8.192

3126H

11.2896

90.3168

6.947446

F28BH

12.288

98.304

7.561846

8FD5H

14.4

11.2896

90.3168

14.4

6.272

45A1H

14.4

12.288

98.304

14.4

6.826667

D3A0H

19.2

11.2896

90.3168

9.6

9.408

6872H

19.2

12.288

98.304

9.6

10.24

3D70H

19.68

11.2896

90.3168

9.84

9.178537

2DB4H

19.68

12.288

98.304

9.84

9.990243

FD80H

19.8

11.2896

90.3168

9.9

9.122909

1F76H

19.8

12.288

98.304

9.9

9.929697

EE00H

11.2896

90.3168

7.5264

86C2H

12.288

98.304

8.192

3126H

11.2896

90.3168

6.947446

F28BH

12.288

98.304

7.561846

8FD5H

11.2896

90.3168

13.5

6.690133

B0ACH

12.288

98.304

13.5

7.281778

4822H

Table 46 PLL Frequency Examples

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