WM8953ECSSLASHRV datasheet(73/100 Pages) WOLFSON

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Production Data

WM8953

PD, January 2009, Rev 4.0

PLL

The integrated PLL can be used to generate SYSCLK for the WM8953 from a wide range of MCLK

reference frequencies. The PLL is enabled by the PLL_ENA register bit. If required, the input

reference clock can be divided by 2 by setting the register bit PRESCALE.

The PLL frequency ratio R is equal to f2/f1 (see Figure 50). This ratio is the real number represented

by register fields PLLN and PLLK, where PLLN is an integer (LSB = 1) and PLLK is the fractional

portion of the number (MSB = 0.5). The fractional portion is only valid when enabled by the field

SDM. De-selection of fractional mode results in lower power consumption.

For PLL stability, input frequencies and divisions must be chosen so that 5

≤ PLLN ≤ 13. Best

performance is achieved for 7

≤ N ≤9. Also, the PLL performs best when f2 is set between 90MHz

and 100MHz.

If PLLK is regarded as a 16-bit integer (instead of a fractional quantity), then PLLN and PLLK may be

determined as follows:

•

PLLN = int R

•

PLLK = int (216 (R - PLLN))

The PLL Control register settings are described in Table 45.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R2 (02h)

PLL_ENA

(rw)

PLL Enable

0 = disabled

1 = enabled

SDM

Enable PLL Integer Mode

0 = Integer mode

1 = Fractional mode

PRESCALE

Divide MCLK by 2 at PLL input

0 = Divide by 1

1 = Divide by 2

R60 (3Ch)

3:0

PLLN[3:0]

Integer (N) part of PLL frequency ratio.

R61 (3Dh)

7:0

PLLK [15:8]

31h

Fractional (K) part of PLL frequency ratio.

(Most significant bits)

R62 (3Eh)

7:0

PLLK [7:0]

26h

Fractional (K) part of PLL frequency ratio.

(Least significant bits)

Table 45 PLL Control

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