WM8953ECSSLASHRV datasheet(28/100 Pages) WOLFSON

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WM8953

Production Data

PD, January 2009, Rev 4.0

INPUT PGA ENABLE

The Input PGAs are enabled using register bits LIN12_ENA, LIN34_ENA, RIN12_ENA and

RIN34_ENA as described in Table 2.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

LIN34_ENA

(rw)

LIN34 Input PGA Enable

0 = disabled

1 = enabled

LIN12_ENA

(rw)

LIN12 Input PGA Enable

0 = disabled

1 = enabled

RIN34_ENA

(rw)

RIN34 Input PGA Enable

0 = disabled

1 = enabled

R2 (02h)

RIN12_ENA

(rw)

RIN12 Input PGA Enable

0 = disabled

1 = enabled

Table 2 Input PGA Enable

REFERENCE VOLTAGES

The analogue circuits in the WM8953 are referenced to VMID (AVDD/2). This voltage is generated

from AVDD via a programmable resistor chain as shown in the audio signal paths diagram on page

15. Together with the external decoupling capacitor on VMID, the programmable resistor chain

results in a slow, normal or fast charging characteristic on VMID. The VMID reference is controlled by

VMID_MODE[1:0].

The analogue circuits in the WM8953 require a bias current. The bias current is enabled by setting

VREF_ENA. Note that the bias current source requires VMID to be enabled also.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

2:1

VMID_MODE

[1:0]

(rw)

00b

VMID Divider Enable and Select

00 = VMID disabled (for OFF mode)

01 = 2 x 50k

Ω divider (Normal mode)

10 = 2 x 250k

Ω divider (Standby mode)

11 = 2 x 5k

Ω divider (for fast start-up)

R1 (01h)

VREF_ENA

(rw)

VREF Enable (Bias for all analogue

functions)

0 = VREF bias disabled

1 = VREF bias enabled

Table 3 Reference Voltages

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