5CEBA2U19C8N datasheet(47/58 Pages) ALTERA

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Configuration Specification

Page 47

June 2013

Altera Corporation

Cyclone V Device Datasheet

AS Configuration Timing

Figure 19 shows the timing waveform for the active serial (AS) x1 mode and AS x4

mode configuration timing.

Table 51 lists the timing parameters for AS x1 and AS x4 configurations in Cyclone V

devices.

The minimum and maximum numbers apply to both the internal oscillator and

CLKUSR

when either one is used as the clock source for device configuration.

The tCF2CD,tCF2ST0,tCFG,tSTATUS, and tCF2ST1 timing parameters are identical to the

timing parameters for passive serial (PS) mode listed in Table 53 on page 1–49.You

can obtain the tCF2ST1 value if you do not delay configuration by externally holding

nSTATUS

low.

Figure 19. AS Configuration Timing Waveform for Cyclone V Devices

Notes to Figure 19:

(1) If you are using AS x4 mode, this signal represents the AS_DATA[3..0] and EPCQ sends in 4-bits of data for each DCLK cycle.

(2) The initialization clock can be from the internal oscillator or the CLKUSR pin.

(3) After the option bit to enable the INIT_DONE pin is configured into the device, INIT_DONE goes low.

Read Address

bit 1

bit 0

bit (n

− 2) bit (n − 1)

tCD2UM

nSTATUS

nCONFIG

CONF_DONE

nCSO

DCLK

AS_DATA0/ASDO

AS_DATA1 (1)

INIT_DONE (3)

User I/O

User Mode

tCF2ST1

tDH

tSU

tCO

(2)

Table 51. AS Timing Parameters for AS x1 and x4 Configurations in Cyclone V Devices—Preliminary

Symbol

Parameter

Minimum

Maximum

Unit

tCO

DCLK falling edge to the AS_DATA0/ASDO output

—

µs

tSU

Data setup time before the falling edge on DCLK

1.5

—

tDH

Data hold time after the falling edge on DCLK

0—

tCD2UM

CONF_DONE

high to user mode

175

437

µs

tCD2CU

CONF_DONE

high to CLKUSR enabled

4 x maximum DCLK period

—

tCD2UMC

CONF_DONE

high to user mode with CLKUSR option on

tCD2CU +(Tinit x CLKUSR

period)

——

Tinit

Number of clock cycles required for device initialization

17,408

—

Cycles

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